processor-design
There are 62 repositories under processor-design topic.
darklife/darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
katef/eurorack-cpu
A CPU implemented in a modular synthesizer
zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.
peilin-chen/Zhulong-RISCV-CPU
CPU Design Based on RISCV ISA
shehanmunasinghe/tinyGPU
tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog
alirezakay/RISC-CPU
A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )
mpskex/chisel-npu
Chisel implementation of Neural Processing Unit for System on the Chip
Amey-Thakur/COMPUTER-ORGANIZATION-AND-ARCHITECTURE-AND-PROCESSOR-ARCHITECTURE-LAB
CSC403: Computer Organization and Architecture [COA] & CSL403: Processor Architecture Lab [PAL] <Semester IV>
AnkurRyder/8085-Processor
8-bit RISC Processor on Logisim
darklife/udarkrisc
u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV
daniel-santos-7/leaf
Um pequeno processador RISC-V de 32 bits desenvolvido com a linguagem de descrição VHDL.
kara-abdelaziz/SEP-CPU
SEP, for Simple Enough Processor, is an elaborated from scratch simulated (on Logisim) educational CPU
rj45/nanogo
NanoGo a Go (golang) Subset for Homebrew / Hobby CPUs
Sooryakiran/Domain-Specific-Hardware-Accelerator-VLSI-CAD-Project
Domain Specific Hardware Accelerators - VLSI CAD Project
JayKaku/RISC-V_MYTH_Workshop
RV32I core using TL-Verilog.This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover
lazyoracle/vhdl-processor
An 8-bit processor in VHDL based on a simple instruction set
Amir-Shamsi/Multicycle-MIPS-in-Verilog
MIPS Multicycle CPU design in Verilog
Bennyaw/SimpleProcessor_Verilog
A simple processor designed using Verilog and Altera DE1 development board.
LeviBohnacker/EDRICO
EDRICO (Educational DHBW RISC-V Core) is a small 32-bit RISC-V core implementing the Integer base architecture and Zicsr extension. It was developed as part of a students project at the DHBW Ravensburg by Noah Wölki and Levi Bohnacker. Future developments (outside of the scope of DHBW Ravensburg) are planned to add further ISA extensions and implement modern processor architectures.
jakujobi/BitBlaster_10bit_Processor
Welcome to the BitBlaster_10bit_Processor! Our custom-designed 10-bit processor, crafted meticulously as part of a project for a Digital Logic Design course at South Dakota State University.
lirui-shanghaitech/EE113_PROCESSOR
The reference design of EE113's final project (Digital integrated Circuit design Fall 2020) at ShanghaiTech University
streetdogg/mips-cpu
Verilog implementation of a subset of MIPS 32 Bit Processor Instructions, ISA design, Assembler Design and Compiler design
0xD503/ARM-Single-Cycle-Processor
ARM architecture single-cycle processor designed according to book "Digital design and computer architecture: ARM edition" as a practice in digital design.
Ajarlin/CS211-Computer-Architecture
Computer Architecture: 01:198:211 This course covers the fundamental issues in the design of modern computer systems, including the design and implementation of key hardware components such as the processor, memory, and I/O devices, and the software/hardware interface.
harmim/vut-inp-project2
Návrh počítačových systémů - Projekt 2 - Procesor s Harvardskou architekturou
helcsnewsxd/famaf-computer_science-computer_architecture-lab1
Laboratorio 1 de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)
KonstantinosVasilopoulos/aueb_processor
A 16 bit processor, following the RISC architecture. Made with Quartus and VHDL.
luisalejandrobf/BoothsAlgorithm
Implementation of Booth's algorithm for signed binary multiplication. It includes code designed for the PDUA processor, developed by the Pontificia Universidad Javeriana. The algorithm is provided in assembly language and includes its translation into executable binary instructions.
nayas360/syn01
Custom processor implemented in logisim-evolution
overengineer/SpecialPurposeProcessor
FPGA implementation of a special purpose processor that performs single operation using custom ALU. You can take look at the [related blog post] (https://overengineer.github.io/SpecialPurposeProcessor) for further details.
tugrul512bit/AdvancedMacroDevices
2D RPG/RTS/Simulation game that lets you design a CPU & manage your corporation against other corporations.
Whitelisted2/CS311-CompArch-Lab
This repository contains files related to Computer Architecture Lab (Autumn 2022).
vbogdev/vbn-Riscv
An attempt at making a 2-way superscalar out-of-order riscv processor for an Arty s25 fpga.
AryaTopale/IPA
In this project, we have programmed a sequential as well as a pipelined processor architecture which includes fetch execute cycle. We have implemented this in Verilog.