BlandoL

BlandoL's Stars

• ZipCPU/wb2axip

  Bus bridges and other odds and ends

  Language:Verilog491101

• OpenXiangShan/XiangShan

  Open-source high-performance RISC-V processor

  Language:Scala4.9k665

• hdl-util/mipi-demo

  MIPI CSI-2 + MIPI CCS Demo

  Language:Verilog6721

• BrooksEE/nitro-parts-lib-mipi

  RTL for mipi serialize and deserialize

  Language:Verilog1110

• lvyufeng/step_into_mips

  一步一步写MIPS CPU

  Language:Verilog750155

• manjushpv/Design-and-Verification-of-Nand-Flash-Memory-Controller

  - Designed a Nand Flash Controller, Flash Memory and Buffer (Design Target : Samsung K9F1G08R0A NAND Flash).
 - Implemented operations : Controller Reset, Memory Erase, Program Page and Page Read.
 - Functional Verification of DUT : Test Plan, Environment Setup, Constraint Randomization, Corner test cases covered.
 - Programming Language : SystemVerilog

  Language:Verilog182

• gyd111/NAND-Flash-controller

  MT29F128G based NAND flash controller

  Language:Verilog8

• cbl709/NAND-Flash-Control

  Language:Verilog114

• grantae/OpenMIPS

  A full implementation of the MIPS32 Release 1 ISA, including virtual memory, TLB, instruction and data caches, interrupts and exceptions, over 100 hw/sw tests, and full ISA compliance

  Language:Assembly6313

• alexforencich/verilog-axi

  Verilog AXI components for FPGA implementation

  Language:Verilog1.5k452

• freecores/dma_ahb

  AHB DMA 32 / 64 bits

  Language:Verilog5021

• adki/gen_amba

  AMBA bus generator including AXI, AHB, and APB

  Language:C9039

• RoaLogic/ahb3lite_interconnect

  AHB3-Lite Interconnect

  Language:SystemVerilog8227

• adki/AMBA_AXI_AHB_APB

  AMBA bus lecture material

  Language:Verilog379126

• whutddk/RiftCore

  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System

  Language:Verilog3511

• ayzk/Simulator_CPU

  Pipeline CPU of MIPS architecture with L1 Data Cache by Verilog

  Language:Verilog217

• SocialistDalao/UltraMIPS_NSCSCC

  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.

  Language:Verilog12121

• mxllc/CPU_StaticPipeline_ThreeLevelCache

  基于静态流水线的三级存储CPU

  Language:Verilog53

• zhaishaomin/ring_network-based-multicore-

  多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency

  Language:Verilog2110

• ronak66/Direct-Mapped-Cache

  Implementation of Direct-Mapped-Cache to hold 256 blocks, 16 32-bit instruction/Data per block with 32-bit address line

  Language:Verilog145

• Lyncien/RISC-V-32I

  体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器

  Language:Verilog6524

• rajshadow/4-way-set-associative-cache-verilog

  Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy

  Language:Verilog4115

• xdesigns/4way-cache

  Verilog cache implementation of 4-way FIFO 16k Cache

  Language:Verilog1910

• airin711/Verilog-caches

  Various caches written in Verilog-HDL

  Language:Verilog11341

• ljlin/MIPS48PipelineCPU

  5 stage pipelined MIPS-32 processor

  Language:Verilog5711

• neelkshah/MIPS-Processor

  5-stage pipelined 32-bit MIPS microprocessor in Verilog

  Language:Verilog11913

• grantae/mips32r1_xum

  A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA. This is a bare-metal CPU with no virtual memory. (Old University of Utah XUM archive)

  Language:Verilog5934

• Trinkle23897/mips32-cpu

  奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）

  Language:Verilog12633

• raiyyanfaisal09/RTL_NAND_Flash_controller

  Language:Verilog158

• ZipCPU/qspiflash

  A set of Wishbone Controlled SPI Flash Controllers

  Language:Verilog7624