Engineer-Ayesha-Shafique/RISC-V-Single-Cycle-Processor
This is a Single Cycle processor running the RV32I implementation, hence a 32-bit CPU, written in SystemVerilog.
SystemVerilog
No issues in this repository yet.
This is a Single Cycle processor running the RV32I implementation, hence a 32-bit CPU, written in SystemVerilog.
SystemVerilog
No issues in this repository yet.