Eyantra698Sumanto

Assist. Project Manager, IIT Bombay | M. Tech. IEOR, IITB | Electronics Engineer, Mumbai University | Interests in VLSI, Optimization, etc.

IIT BombayMumbai, India

Pinned Repositories

avsdspamp_3v3_sky130
41
BASIC-JAVA-PROGRAMS-3
This Repository contains basic programs in JAVA programming language.
Language:Java2 1 00
Digital-Design-on-FPGA
This repo contains documentation of the "VSD Open Digital-Design-on-FPGA" tutorial.
3 1 01
Spice-to-Verilog-Converter
Spice to Verilog Converter
Language:Python11 1 11
VSDOpen_PLL_Tutorial
This repo contains documentation of the "VSD Open On-Chip Clock Multiplier (PLL) on OSU180" tutorial.
4 1 01
XOR-XNOR-Gate
Language:Verilog4 1 012
eSim
This repository contain source code for new flow of FreeEDA now know as eSim
Language:Python84 27 6173
LTSpiceToKiCadConverter
Language:Python2 5 02
OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Language:Python1.3k 59 947369
riscv-ctb-challenge-Eyantra698Sumanto
riscv-ctb-challenge-Eyantra698Sumanto created by GitHub Classroom
Language:C01

Eyantra698Sumanto's Repositories

Eyantra698Sumanto/Spice-to-Verilog-Converter
Spice to Verilog Converter
Language:Python11 1 11
Eyantra698Sumanto/eSim-IP-Library
Language:C++1 0 0
Eyantra698Sumanto/eSim_PSpice_to_KiCad_Python_Parser
Language:Python1 0 0
Eyantra698Sumanto/ajit-toolchain
Toolchains for AJIT Processor IIT Bombay
Language:C
Eyantra698Sumanto/BeGAN-benchmarks
0 0
Eyantra698Sumanto/caravel
Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.
Language:Verilog
Eyantra698Sumanto/Caravel-AI-RISCV-Timer
Language:Verilog
Eyantra698Sumanto/caravel_avsdspamp_3v3_sky130
Language:Verilog1 0
Eyantra698Sumanto/caravel_dvsdfossbfc
Language:Verilog
Eyantra698Sumanto/conductor
Conductor is an event driven orchestration platform
Eyantra698Sumanto/DLProject-Discrete-Diffusion-for-Image-Captioning
Language:Jupyter Notebook
Eyantra698Sumanto/DuinoMusic
Eyantra698Sumanto/eSim
This repository contain source code for new flow of FreeEDA now know as eSim
Language:Python0 0
Eyantra698Sumanto/esim-general
basic reference files for esim simulation
Eyantra698Sumanto/Eyantra698Sumanto
1 0
Eyantra698Sumanto/gf180mcu-pdk
PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).
Eyantra698Sumanto/IHP-Open-PDK
130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
Eyantra698Sumanto/kicp
The Knight Innovation Co-Processor
Language:Verilog0 0
Eyantra698Sumanto/LTSpiceToKiCadConverter
Language:Python
Eyantra698Sumanto/mayavi
3D visualization of scientific data in Python
Language:Python0 0
Eyantra698Sumanto/QSim_ALU
This repository contains Qiskit code to simulate an ALU using QSim
Language:Jupyter Notebook
Eyantra698Sumanto/quantum_computing_course2023
Course Material for the online short course on Quantum Computing Using QSim
Language:Jupyter Notebook0 0
Eyantra698Sumanto/qucs_s
Qucs-S provides GUI for different circuit simulation kernels.
Language:C++0 0
Eyantra698Sumanto/README.md
Eyantra698Sumanto/riscv-Eyantra698Sumanto
riscv-ctb-challenge-Eyantra698Sumanto created by GitHub Classroom
Eyantra698Sumanto/siliconcompiler
A modular build system for hardware
Eyantra698Sumanto/skywater-pdk
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
Eyantra698Sumanto/Slides2Notes
Language:Jupyter Notebook
Eyantra698Sumanto/sscs-ose-chipathon.github.io
Language:Jupyter Notebook
Eyantra698Sumanto/sscs-ose-code-a-chip.github.io
IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)