/RISC-V-Pipelined-Processor-with-CSR

3-stage RISC-V Pipelined Processor with interrupt CSR support

Primary LanguageSystemVerilog

RISC-V-Pipelined-Processor-with-CSR

A 3-stage Pipelined Processor written from scratch in SystemVerilog for executing the machine code of RISC-V ISA with interrupt CSR (Control and Status Register). RISC-V is an open standard instruction set architecture based on established reduced instruction set computer principles.

Instruction Types

The instruction types implemented in this project are:

  • R-type
  • I-type
  • S-type
  • B-type
  • J-type
  • U-type
  • CSRRW
  • MRET

Support this project by leaving a ⭐