HalfVulpes's Stars
cggos/shenlan_vio_course
深蓝学院《视觉SLAM进阶:从零开始手写VIO》第一期
gaoxiang12/slambook
maswx/vu13p
国产VU13P加速卡资料
d953i/SQRL_FK33
SQRL FK33 board files, example designs and scripts.
Gralerfics/FmcPGA
A pseudo Minecraft game running on Artix-7 FPGA in VHDL. Also the final project for SUSTech EE332-Digital-System-Designing.
2noise/ChatTTS
A generative speech model for daily dialogue.
devinatkin/tt07-dual-oscillator
Two Oscillator Outputs 20Mhz, 21Mhz Target Frequencies
stamcenter/Trireme_Platform
SI-RISCV/e200_opensource
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
riscv-mcu/e203_hbirdv2
The Ultra-Low Power RISC-V Core
ultraembedded/biriscv
32-bit Superscalar RISC-V CPU
risclite/SuperScalar-RISCV-CPU
SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
eembc/coremark
CoreMark® is an industry-standard benchmark that measures the performance of central processing units (CPU) and embedded microcrontrollers (MCU).
DHDAXCW/OpenWrt_RockChip
基于 lede-rockchip 源码建构 rockchip 的 OpenWrt 固件。
liangkangnan/tinyriscv
A very simple and easy to understand RISC-V core.
LoveLonelyTime/Bergamot
An exquisite superscalar RV32GC processor.
litex-hub/linux-on-litex-vexriscv
Linux on LiteX-VexRiscv
enjoy-digital/litex
Build your hardware, easily!
SpinalHDL/VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
SanjayRai/SRAI_HW_ACCEL_WINDOWS10_PCIe
PCIe based accelerator for VCU1525 with xDMA based on Windows10 and Windows Server 2016 development environment
Xilinx/dma_ip_drivers
Xilinx QDMA IP Drivers
gangweiX/ACVNet
[CVPR 2022] ACVNet: Attention Concatenation Volume for Accurate and Efficient Stereo Matching
google-research/google-research
Google Research
ibaiGorordo/HITNET-Stereo-Depth-estimation
Python scripts for performing stereo depth estimation using the HITNET Tensorflow model.
xiangfuli/STM32_freeRTOS_CMake_template
This project is an initial project template for programming STM32F4 devices with FreeRTOS support
tow3rs/catapult-v3-smartnic-re
Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)
espressif/esp-idf
Espressif IoT Development Framework. Official development framework for Espressif SoCs.
wentaoyuan/deepgmr
PyTorch implementation of DeepGMR: Learning Latent Gaussian Mixture Models for Registration (ECCV 2020 spotlight)
Qv2ray/Qv2ray
:star: Linux / Windows / macOS 跨平台 V2Ray 客户端 | 支持 VMess / VLESS / SSR / Trojan / Trojan-Go / NaiveProxy / HTTP / HTTPS / SOCKS5 | 使用 C++ / Qt 开发 | 可拓展插件式设计 :star:
jofrfu/tinyTPU
Implementation of a Tensor Processing Unit for embedded systems and the IoT.