Issues
- 1
Add support for the use of regfiles in swregs
#719 opened by AndreMerendeira - 3
merge hex_split.py and makehex.py
#760 opened by jjts - 0
fix(CDC): axistream in
#966 opened by P-Miranda - 4
- 1
fix simulation (icarus) and synthesis (yosys) errors
#952 opened by jjts - 0
Confs attribute "val" is not validated (does not test if it between min and max)
#837 opened by AndreMerendeira - 1
Support multiple clocks for Verilator Simulation
#949 opened by P-Miranda - 6
iob_r input/output signals {iob_r_data_i/o} should be renamed do data_i/o
#948 opened by AndreMerendeira - 1
clang format
#947 opened by jjts - 2
do not update define /if_gen
#605 opened by jjts - 1
elimeinate always @posege clk
#762 opened by jjts - 2
generate all interfaces using if_fgen.py
#763 opened by jjts - 5
IOb-SoC firmware start address and size.
#814 opened by arturum1 - 1
iob-soc revamp
#769 opened by jjts - 1
- 0
false parameters should not appear in docs /if_gen2
#867 opened by arturum1 - 2
unneeded code /if_gen
#631 opened by jjts - 6
Eliminate setup.mk
#761 opened by jjts - 2
should be iob_interface like the others
#804 opened by jjts - 2
incomprehensible code snippet /if_gen
#629 opened by jjts - 4
Vivado.log critical errors related to the Ethernet and the "clk" constrains
#611 opened by PedroAntunes178 - 2
user unfriendly method /if_gen
#606 opened by jjts - 1
call a miniimum of iob_module class methods
#766 opened by jjts - 1
Vivado does not stop on timing fails
#649 opened by AndreMerendeira - 3
remove basic and, or, inv, aoi modules
#818 opened by jjts - 3
mkregs should have an opetion to connect the insance ports to the modules' ports /if_gen
#621 opened by jjts - 5
create_wrapper_files
#759 opened by jjts - 1
range in single bit signals
#850 opened by jjts - 3
- 1
Deprecate IOB_REQ and IOB_RESP macros
#768 opened by jjts - 1
- 1
- 2
- 2
.sdc files for the CSR interfaces should be added to the LIB syn/src folder instead of each core having to repeat them (available and tested in iob-i2s-tdm)
#718 opened by AndreMerendeira - 1
delete pre-setup /if_gen
#632 opened by jjts - 0
change verilog snippets sysntax
#851 opened by jjts - 0
no interfaces in submodules list /if_gen
#630 opened by jjts - 0
make clean bug
#830 opened by AndreMerendeira - 4
deprecate the flows variable
#765 opened by jjts - 1
- 1
- 0
macros in _conf.[v]h should have core name prefix
#626 opened by jjts - 0
mkregs address macros same name as constants
#618 opened by jjts - 1
make boot controller a peripheral
#527 opened by jjts - 0
- 8
run on xilinx zynq
#562 opened by zchliu - 0
quartus and vivado losg thrown in the upper directory
#519 opened by jjts - 0
- 2
- 0
DCACHE_ADDR_W to become MEM_ADDR_W
#529 opened by arturum1