[compilation bug] Width mismatch not caught by the semantic analyzer

[Jacajack]

Input

048_width_deduced_in_generic_from_generic

module y{
	int a;
	input const ubus<(a*4)> d;
}
impl y{}

module x{
	int a;
}

impl x{
	y mm{
		a: a*2,
		d: const auto dd
	}
	dd = 0u2; // FIXME ext() does not work here
}

module m{}
impl m{
	x xx{
		a: 1,
	}
}

Output

module m;
        localparam logic signed[63:0] xx_instance_a_generic = 64'sh1;

        x        #(
                .a(xx_instance_a_generic)
        )
         xx      (
        )       ;


endmodule
module y #(
        parameter logic signed[63:0] a
)(
        input wire unsigned[((a * 4) - 1):0] d
);

endmodule
module x #(
        parameter logic signed[63:0] a
);
        localparam logic signed[63:0] mm_instance_a_generic = ((128)'(a) * (128)'(64'sh2));

        wire unsigned[(((a * 2) * 4) - 1):0] dd;
        wire unsigned[(((a * 2) * 4) - 1):0] mm_instance_d;

        assign mm_instance_d = dd;
        assign dd = 2'h0;

        y        #(
                .a(mm_instance_a_generic)
        )
         mm      (
                .d(mm_instance_d)
        )       ;


endmodule
During elaboration the following diagnostics were generated:

  ⚠ Warning: Signal is not being used
   ╭─[tests/input/048_width_deduced_in_generic_from_generic.hirl:2:1]
 2 │     int a;
 3 │     input const ubus<(a*4)> d;
   ·                             ┬
   ·                             ╰── This signal is never being used
 4 │ }
   ╰────

Expected

The compilation should fail. In that instance dd is 8 bits wide and the assigned value is only two bits wide. Semantic analyzer should catch that case.

Caught in elab on the #309 branch.

[WojciechPtas]

Root cause:
because width of dd emerges from inside of module, it is save internally as Evaluable. but in fact it should be safed as EvaluatedLocated , so that further semantical analysis can be performed