JieGH
FPGA, SIMD, Embedded Sys., AI. APROPOS Project, Marie Skłodowska-Curie Actions Researcher https://www.apropos-itn.eu/
Europe
JieGH's Stars
crissmath/Thesis_DISCA_template
Plantilla PHD thesis DISCA, Doctorado en Informatica.
ECASLab/cynq
PYNQ bindings for C and C++ to avoid requiring Python or Vitis to execute hardware acceleration.
google/XNNPACK
High-efficiency floating-point neural network inference operators for mobile, server, and Web
google/gemmlowp
Low-precision matrix multiplication
m516/TinyMatrixMath
This modern, cross-platform library is a collection of functions and classes for doing math on small matrices with limited resources
aproposorg/hard_sydr
Benchmarking GNSS system at the Xilinx PYNQ FPGA based platform
Xilinx/mlir-aie
An MLIR-based toolchain for AMD AI Engine-enabled devices.
Brendan-Kirtlan/Video-Encode
Encodes a file into a video format to store on a cloud video hosting service
hansemandse/vitisfft
Template for implementing array-interfaced FFTs with Vitis HLS
spcl/hls_tutorial_examples
Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
sysprog21/rv32emu
Compact and Efficient RISC-V RV32I[MAFC] emulator
openhwgroup/riscv-ovpsim-corev
riscv-software-src/riscv-tests
chipsalliance/riscv-dv
Random instruction generator for RISC-V processor verification
openhwgroup/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
riscv-verification/RVVI
RISC-V Verification Interface
ahmad-mirsalari/PULP
A public repository discussing the PULP (Parallel Ultra Low Power) platform for open-source RISC-V processors and associated software.
openhwgroup/cv32e40x
4 stage, in-order, compute RISC-V core based on the CV32E40P
apple/ml-stable-diffusion
Stable Diffusion with Core ML on Apple Silicon
riscv-software-src/riscv-isa-sim
Spike, a RISC-V ISA Simulator
riscv-collab/riscv-gnu-toolchain
GNU toolchain for RISC-V, including GCC
goossens-springer/goossens-book-ip-projects
this repository contains all the ip projects presented in the HLS/RISC-V/Computer Architecture book written by Goossens and published by Springer
aproposorg/c_sydr
C/C++ implementation of the SyDR library.
KULeuven-MICAS/stream
Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
ferrandi/PandA-bambu
PandA-bambu public repository
ripperhe/Bob
Bob 是一款 macOS 平台的翻译和 OCR 软件。
aproposorg/KV260-PYNQ-tutorial
Simple PYNQ KV260 tutorial: Porting C-based design into FPGA via Xilinx HLS
MEVIUS-FPT/hls_traffic_light_recognition
Traffic Light Recognition with High-Level Synthesis
DYGV/hls_traffic_light_recognition
Traffic Light Recognition with High-Level Synthesis
DYGV/HLS_FFT
Design of High-Level Synthesis of Xilinx FFT IP core via FFT library