Pinned Repositories
alchitry-verilog-exercises
Sequence of exercises used to learn Verilog on Alchitry Au FPGA
beneater-8bit-computer
Implementation of Ben Eater's design for an 8 bit breadboard computer
gtestverilog
Extension to GoogleTest for working with Verilog designs
nandland-verilog-exercises
Verilog Go Board Exercises from https://www.nandland.com/goboard/index.html
opencv-project1
Short Project with opencv & Face Detection
profile
C++ Intrusive Function Profiling Library
profile-visualiser
Visualise Function Profiler Logs
SpaceInvaders8080
Software Emulation of Intel 8080 CPU for Taito Space Invaders Arcade Game
verilog-nes
Building a Nintendo Entertainment System in Verilog
verilog-spi
Unit Tested implementation of SPI protocol in verilog
JimKnowler's Repositories
JimKnowler/SpaceInvaders8080
Software Emulation of Intel 8080 CPU for Taito Space Invaders Arcade Game
JimKnowler/profile
C++ Intrusive Function Profiling Library
JimKnowler/verilog-nes
Building a Nintendo Entertainment System in Verilog
JimKnowler/profile-visualiser
Visualise Function Profiler Logs
JimKnowler/verilog-spi
Unit Tested implementation of SPI protocol in verilog
JimKnowler/alchitry-verilog-exercises
Sequence of exercises used to learn Verilog on Alchitry Au FPGA
JimKnowler/beneater-8bit-computer
Implementation of Ben Eater's design for an 8 bit breadboard computer
JimKnowler/nandland-verilog-exercises
Verilog Go Board Exercises from https://www.nandland.com/goboard/index.html
JimKnowler/opencv-project1
Short Project with opencv & Face Detection
JimKnowler/picamera
A pure Python interface to the Raspberry Pi camera module
JimKnowler/gtestverilog
Extension to GoogleTest for working with Verilog designs
JimKnowler/dvb_capture
Exercise in processing Transport Stream broadcast over DVB-T
JimKnowler/formalmethods-zipcpu-class-verilog
Verilog Examples and exercises from ZipCPU's formal methods class
JimKnowler/icebreaker-verilog
Working with IceBreaker FPGA on MacOS
JimKnowler/pipelined-cpu
Experimenting with writing a 5 stage pipelined CPU in verilog
JimKnowler/rules_verilator
Bazel build rules for Verilator
JimKnowler/Sock-Puppets
JimKnowler/spike-discordbot
Spiking a basic discord bot
JimKnowler/spike-midi-input-interface
Experiment in building a midi input circuit
JimKnowler/Spike-PixelGameEngine
Quick spike with OlcPixelGameEngine for HackHorsham 11th Jan 2020
JimKnowler/spike-python-opencv
Series of short spikes of OpenCV features for the purpose of revising python OpenCV API.
JimKnowler/spike-uart
Experiment in reading/sending UART serial comms
JimKnowler/spike-verilator-fpga
Initial experiments in using 'verilator' to generate C++ simulations of Verilog designs
JimKnowler/tinyfpga-verilog-exercises
Learning Verilog programming with TinyFPGA-Bx
JimKnowler/vivado-cpu6502-debugger
Replica of 6502 CPU running in a debugger framework on Vivado/ARTY-A7
JimKnowler/vivado-nes-debugger
Vivado project for debugging NES design