NASSCOM–VSD SoC Design Workshop

2 weeks workshop on Digital VLSI using Sky130 PDK

📑 Table of Contents

Introduction
Magic Tool Overview
Linux Commands Used
Lab 1 – Opening OpenLane
Lab 2 – Synthesis & Floorplan
Layout Creation in Magic
Placement
Custom Inverter Layout
CMOS Cross-Section
SPICE Simulation
Conclusion

Overview

Tools Used: OpenLANE, Magic, ngspice, OpenROAD
PDK: SkyWater SKY130A (130 nm open-source)
Design Used: picorv32a (RISC-V Core)
Duration: 2 weeks (structured 5 + 5 days)
Environment: Oracle VM (Ubuntu)

Free and Open Source Software (FOSS) and Free And Open Source Silicon (FOSSi) EDA tools and opensource being an advantage.The workshop includes short videos and gives a good understanding for how chip design process forks.It tells how ASIC design flow works with more emphasis on the Back-End. The Back-End usually involves steps like Synthesis,STA of the .v file then Design for Testability (DFT), Physical Design, then Physical Verification and finally the GDS-II file creation.Gds is the file saving format given to the foundries and normally it is in binary involving geometric shapes.

VLSI which stands for Very Large Scaling Industry refers to the scaling of size and increment of the transistors numbers on a single chip.

Further more chip architecture was discussed along with basic CMOS(complementary metal oxide semiconductor technology) concept that tells the reason for the steps done in the backend. Further more the workshop was equipped with the labs and assignment as well, which gives hands on experience, and practical insights of the backend process.

This 2-week workshop provides a structured introduction to digital VLSI design using Free and Open Source Software (FOSS) and Silicon (FOSSi). The video lectures were organized in a nested format, for example:

Sky130 Day 3 – Design library cell using Magic Layout and ngspice characterization * SKY130_D3_SK2 – Inception of Layout – CMOS fabrication process * SKY_L9 – Lab steps to create std cell layout and extract spice netlist

We explored fundamental concepts like VLSI (Very Large Scale Integration), CMOS technology, and chip architecture, all reinforced with hands-on labs and assignments. From the image below, our workshop is more focused toward Team B (Physical Design). Labs along with the assessments are conducted. Linux System and Commands were used throughout the workshop period. In the figure given below please mark layout instead of layoiut.

Virutal machine by oracle is utilized as most of the VLSI tools are based on linux so it provides isolated environment for working effectively.Linux has more advantage and for critical process like chip design which is the brain of any device or machine is a preferred choice.This documentation is more of picture based (means do the steps by keeping the images as a reference in your mind) so follow accordingly.

Magic Tool Overview

As per Fossi Dial up Magic tool is more than DRC, it can read and write GDS.It can extract and netlist (SPICE file).LEF(Library Exchange File)/DEF(Design Exchange File) compatible.Wiring refers to physical joining of the network elements whereas routing defines rules for that.This feature is also included in the Magic.Plots are available for the analysis of the results in a graphical manner. More features

Paint and Erase
Instead of bins it works on single base

Introduction

The workshop emphasized FOSSi (Free and Open-Source Silicon Initiative) and demonstrated how open-source EDA tools democratize chip design.

It followed the complete ASIC design flow:

Synthesis
Floorplanning
Placement
Clock Tree Synthesis (CTS)
Routing
Static Timing Analysis (STA)
Physical Verification (DRC/LVS)
GDS-II generation

Each step was practically implemented using OpenLANE automation, Magic layout, and ngspice simulation:

Oracle VM VirtualBox used for isolated Linux environment
Linux OS preferred for chip design reliability
Magic – layout editing, DRC/LVS, GDSII generation
ngspice – circuit simulation
OpenLane – RTL-to-GDSII flow

Lab 1 : To open the openflow

type docker
type second command ./flow.tcl -interactive

Linux commands used:

cd    // to change directory 
ls    // to list items
ltr   // list in chro order
pwd   // shows current directory
cd ../  // makes the directory levele two step up

LAB 2: To run Synthesis and Floorplan

after openlane is opened, type command prep -design picorv32a The success preperation message will look like below

The folder with timestamp is created where all of the results for the design is stored

The picorv32a design compilation

The synthesized results are seen by less command

Assessment 1 flop ratio

Equals to 10.84 percentile

Assessment 2 area of the die

die height and die width calculation by subtracting down leftmost corner from top rightmost corner == 443587.2122325 in microns square

Lab: To create layout of the picorv32a

In the results directory of the floorplan open it in the terminal and type command: magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.floorplan.def &

from zooming the blocks are seen with its unique role in overall

Placement again the synthesis process is followed in sequence creating folder named 28-04-11:55 to run_placement

Further more the equidistant nature is changed for some reason and below files are again revisied

git cloning step for the custom inverter

n and p well is identified by clicking on the S and by arrow keys for navigating it

the cloned repositry explains the steps involved for the RTL to GDSII flow

deleting part of an area thus getting an error in DRC which is indicated by red colour
creation of spice file by running following commands in the tkcon terminal with the inverter being not modified

pwd
extract all                      // this will make .ext file
ext2spice cthresh 0 thresh 0     // this will extract parasitics 
ext2spice                          // finally spice file will be created by this commant

now going to the window option set the 0.10 micro metre grid now zoom in and do the selection of the box and run the command box

next step would be editing the spice file

this is the image of the 16 mask cmos process from p substrate tp the final stage that after opening the contact holes which is not discussed in the video although might be a good homework.

the image describes how drain of pmos and nmos are connected together

this image shows how source of pmos is connected to the ground,and next task would be to know where is drain of nmos here

how they relates pdiff/ndiff is similar to the implants in the cross sectional view of the cmos
getting back to spice
earlier the spice file for the inverter was created without the parasitcs of cap and res
use 'vim sky130_inv.spice'
to read the file
The spice code understaning whose screenshot can be seen by going up

.option scale=10m

.subckt sky130_inv A Y VPWR VGND
X0 Y A VGND VGND sky130_fd_pr__nfet_01v8 ad=1.44n pd=0.152m as=1.37n ps=0.148m w=35 l=23
X1 Y A VPWR VPWR sky130_fd_pr__pfet_01v8 ad=1.44n pd=0.152m as=1.52n ps=0.156m w=37 l=23
C0 VPWR A 0.0774f
C1 Y A 0.0754f
C2 VPWR Y 0.117f
C3 Y VGND 0.279f
C4 A VGND 0.45f
C5 VPWR VGND 0.781f
.ends
~

X1 Y A VPWR VPWR sky130_fd_pr__pfet_01v8 ad=1.44n pd=0.152m as=1.52n ps=0.156m w=37 l=23
if you see this line the X is used to instantiate the subcircuit (in our case it is of pfet) that is present inside the sky130 pdk. also,

sky130 → SkyWater 130nm process
fd → Fully Depleted (not relevant here; historical)
pr → Primitive device (used in layout and simulation)
pfet → P-type Field Effect Transistor = PMOS
01v8 → Designed for 1.8V nominal operation (core voltage domain in CMOS)

removing subcircuit portion from the generated spice code and adding spice code as per feroz repositry take as reference

after certain modification in the spice code
the output was:

expected output is

Further more for measuring the delay values we use the below commands:
Rise and Fall Time Calculation:

#Rise transition time calc
.meas tran t10 TRIG v(out) val = 0.18 RISE = 1;
.meas tran t80 TRIG v(out) val = 1.44 RISE = 1;
.meas tran trise PARAMS = 't90 - t10';

#Fall transition time calc
.meas tran t80f TRIG v(out) val = 1.44 FALL = 1;
.meas tran t10f TRIG v(out) val = 0.18 FALL = 1;
.meas tran tfall PARAMS = 't10f - t90f';

Downloading the drc by using the following command to perform drc violations fixing:

wget http://opencircuitdesign.com/open_pdks/archive/drc_tests.tgz
tar xfz drc_tests.tgz
gvim .magicrc
magic -d XR &

certain modificiations were done, so to mark the error, which was hidden. next we have to fix N-Well, which was overlapping the Deep N-well and the dimensions which was needed to be added was 0.4 micrometre, so to fix this error.

Given below is the tracking information, which are metal traces used for routing.
from this we can find the pitch values, or number of grid boxed inside the selected outer box.

in the tkcon window we have used the `grid` command and setted the values as ``` grid 0.46um 0.34um 0.23um 0.17um ``` which are similar to the values finded out in the routing file. Furthermore, we looked upon 3 conditions which we have to remember: intersection, width to be odd multiple and height have to be even multiple.

Next, we were exposed to how ports are named and attached to the layout files (Magic ignores the port definations, but it is useful for placement)

then, we saved it as custom inverter with the name sky130_vsdinv, which we will use in the future placements and routing stages.

then we, checked the config.tcl file and edited it by adding the following commands:

set ::env(LIB_SYNTH) "$::env(OPENLANE_ROOT)/designs/picorv32a/src/sky130_fd_sc_hd__typical.lib"
set ::env(LIB_FASTEST) "$::env(OPENLANE_ROOT)/designs/picorv32a/src/sky130_fd_sc_hd__fast.lib"
set ::env(LIB_SLOWEST) "$::env(OPENLANE_ROOT)/designs/picorv32a/src/sky130_fd_sc_hd__slow.lib"
set ::env(LIB_TYPICAL) "$::env(OPENLANE_ROOT)/designs/picorv32a/src/sky130_fd_sc_hd__typical.lib"

set ::env(EXTRA_LEFS) [glob $::env(OPENLANE_ROOT)/designs/$::env(DESIGN_NAME)/src/*.lef]

rerunning the openlane flow so, to check the command for overwriting the existing file in the same directory, and after preparing our design we are supposed to add the following commands:

# commands to load merged.lef having our custom inverter
set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
add_lefs -src $lefs

# Know more about synth strategy from the readme.md file located in the openlane 
echo $::env(SYNTH_STRATEGY)

# Command to set new value for SYNTH_STRATEGY from AREA "0"
set ::env(SYNTH_STRATEGY) "DELAY 3"

# Command to display current value of variable SYNTH_BUFFERING to check whether it's enabled
echo $::env(SYNTH_BUFFERING)

# Command to display current value of variable SYNTH_SIZING
echo $::env(SYNTH_SIZING)

# Command to set new value for SYNTH_SIZING from 0
set ::env(SYNTH_SIZING) 1

# Command to display current value of variable SYNTH_DRIVING_CELL to check whether it's the proper cell or not (sky inverter )
echo $::env(SYNTH_DRIVING_CELL)

then we run run_synthesis command followed by placement and we get our Total Negative Slack value as -759.46 and Worst Negative Slack value as -24.89 in ns. These violations are expected to be fixed.

we, have confirmed the custom inverter from the merged.lef file

Few errors like in the image and is solved by using the commands

init_floorplan
place_io
tap_decap_or

Resizer.lib error which was solved by moving the required file to the project directory.

then we use run_placement command

Using magic we have confirmed the placement of our custom inverter. ``` magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.placement.def & ```

then, we note the capacitance value for using it in the sdc written by us. We have also created pre_sta.conf file for Static Timing Analysis by using the command sta pre_sta.conf

then we, use replace_cell <cell_name> <new_cell_name> command to reduce the slack by noting the cells having the most delay and fanout and replacing them from the alternatives of it from the library.

command for the report reading ```report_checks -fields {net cap slew input_pins} -digits 4 exit```

slack reduced by 1.8ns. It was achieved through noting the cell number in _ _ format and making the changes accordingly.

it is a crucial stage to complete it by using write_verilog <synthesized netlist name eg. picorv32.v> command after the possible slack reductions.

It is noted that even without saving our Chip area for module was '\picorv32a': 181730.544000 and tns 0.00 wns 0.00 which was ideal, but how it came is the challenge which is not in the scope of this project currently.

then, we ran run_cts by Triton for Clock Tree Synthesis, which will create the paths by using most likely the H Algorithm.

Checking the file present inside configuration folder, for variables definations:

then, we used, read_lef and read_def commands for POST CTS (1):

# Command to run OpenROAD tool
openroad

# Reading lef file
read_lef /openLANE_flow/designs/picorv32a/runs/04-10_10-12/tmp/merged.lef

# Reading def fileOP
read_def /openLANE_flow/designs/picorv32a/runs/04-10_10-12/results/cts/picorv32a.cts.def

# Creating an OpenROAD database to work with
write_db pico_cts.db

# Loading the created database in OpenROAD
read_db pico_cts.db

# Read netlist post CTS
read_verilog /openLANE_flow/designs/picorv32a/runs/04-10_10-12/results/synthesis/picorv32a.synthesis_cts.v

# Read library for design
read_liberty $::env(LIB_SYNTH_COMPLETE)

# Link design and library
link_design picorv32a

# Read in the custom sdc we created
read_sdc /openLANE_flow/designs/picorv32a/src/base.sdc

# Setting all cloks as propagated clocks
set_propagated_clock [all_clocks]

# Check syntax of 'report_checks' command
help report_checks

# Generating custom timing report
report_checks -path_delay min_max -fields {slew trans net cap input_pins} -format full_clock_expanded -digits 4

# Exit to OpenLANE flow
exit

below are the screenshots of the each commands:

we checked the slack value once again:

echo $::env(CTS_CLK_BUFFER_LIST)

# Removing 'sky130_fd_sc_hd__clkbuf_1' from the list
set ::env(CTS_CLK_BUFFER_LIST) [lreplace $::env(CTS_CLK_BUFFER_LIST) 0 0]

# Checking current value of 'CTS_CLK_BUFFER_LIST'
echo $::env(CTS_CLK_BUFFER_LIST)

# Checking current value of 'CURRENT_DEF'
echo $::env(CURRENT_DEF)

# Setting def as placement def
set ::env(CURRENT_DEF) /openLANE_flow/designs/picorv32a/runs/04-10_10-12/results/placement/picorv32a.placement.def

# Run CTS again
run_cts

# Checking current value of 'CTS_CLK_BUFFER_LIST'
echo $::env(CTS_CLK_BUFFER_LIST)
# then we re run the POST CTS (1) commands ran earlier, to observe changes

make sure to add the following commands:

# Generating custom timing report report_checks -path_delay min_max -fields {slew trans net cap input_pins} -format full_clock_expanded -digits 4

Report hold skew

report_clock_skew -hold

Report setup skew

report_clock_skew -setup

Power Distribution Network And Routing

A PDN (or Power Distribution Network) is the complete path that delivers power from the supply to each transistor inside a chip. It includes wires, PCB traces, bumps, package pins, on-chip metal layers, and vias.

Along this path, resistance, capacitance, and inductance cause the voltage at the transistors to drop or fluctuate (not perfectly equal to the power supply). [sourced_https://semiengineering.com/knowledge_centers/low-power/low-power-design/power-delivery-network-pdn/]

Commands used:

gen_pdn
magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read 18-pdn.def &
#commands can be different so always cross-check

then, we ran run_routing for detailed routing.

magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.def &

Parasitics Exxtraction

Creating the environment for SPEF_EXTRACTOR:

We encountered the parsing error:

and fixed it by going to the lef_util.py file and make the following changes in line number 380

then, we ran the below command for the extraction process:

python3 main.py /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/04-10_10-12/tmp/merged.lef /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/04-10_10-12/results/routing/picorv32a.def

whose result is seen below: