the purpose of this platform is two folds:
- make FPGA and system design easier
- validate reflow at a bigger scale
- abus
- ports
- sram
- adder_cla
- adder_rca
- comp_eq
- comp_gt
- comp_lt
- gray_counter
- multiplier_booth_4
- multiplier_comb
- resync + clock mux
- fir
- sinus
- cosinus
- viterbi decoder
- fcounter
- jtag_sib
- jtag_tdr
- jtag_fsm
- oscillator
- timer
- adc_sar