Pinned Repositories
FSMD-NIOS-II-SoC-and-ARM-Cortex-M0-SoC
This project aims to compare the performance of Implementing 3x3 Matrix multiplier using three different implementations (FSMD, NIOS II SoC, and ARM Cortex M0 SoC) from three different approaches: functional simulation, timing analysis, and execution time. Then, configuring the three implementations on Cyclone® IV FPGA device.
-A-32-bit-5-stage-Pipelined-MIPS-based-RISC-Core-based-on-Harvard-Architecture-
This project aims to implement a 32-bit 5-stage pipelined High-performance MIPS-based RISC Core based on Harvard Architecture. The MIPS processor was designed using MIPS ISA (Instruction Set Architecture) and divided into three main modules: datapath unit, control unit, and hazard unit. The processor is tested to run two programs: GCD Calculation of two numbers and Factorial Calculation of a number. Programs are written in MIPS assembly code, then converted to machine code. Verilog HDL language is used on ModelSim Simulation tool to verify the functional simulation of the processor and compare between five-stage pipelined MIPS processor and single-cycle MIPS processor regarding performance analysis. Keywords: Pipelined MIPS Processor, Harvard Architecture, MIPS Assembly, Functional Simulation, Datapath, Hazard Unit.
Digital-Design-System
It is responsible for doing some processing using ALU block on Register File stored data to generate byte data then add CRC bits to generate a packet and send it using Serial Communication Protocol UART
Single-Cycle-MIPS-Processor-
The aim of this project is to design a 32-bit single-cycle MIPS processor for RISC (Reduced Instruction Set Computer) processor. The MIPS processor was designed using MIPS ISA (Instruction Set Architecture) and divided into two parts: the datapath unit, and the control unit. Verilog HDL language to design hardware modeling is used on ModelSim tool. Keywords: MIPS, RISC, ISA, datapath, Verilog.
Simplified-Processor-Module
Restaurant-Management
Advanced-Encryption-Standard-AES-
A-simple-game-application
Assembly-Game
A-32-Bit-5-Stage-Pipelined-MIPS-based-RISC-Core-based-on-Harvard-Architecture.
This project aims to implement a 32-bit 5-stage pipelined High-performance MIPS-based RISC Core based on Harvard Architecture. The MIPS processor was designed using MIPS ISA (Instruction Set Architecture) and divided into three main modules: datapath unit, control unit, and hazard unit. The processor is tested to run two programs: GCD Calculation of two numbers and Factorial Calculation of a number. Programs are written in MIPS assembly code and then converted to machine code. Verilog HDL language is used on ModelSim Simulation tool to verify the functional simulation of the processor and compare between five-stage pipelined MIPS processor and single-cycle MIPS processor regarding performance analysis. Keywords: Pipelined MIPS Processor, Harvard Architecture, MIPS Assembly, Functional Simulation, Datapath, Hazard Unit.
Mostafa-Hassanien's Repositories
Mostafa-Hassanien/Advanced-Encryption-Standard-AES-
Mostafa-Hassanien/-A-32-bit-5-stage-Pipelined-MIPS-based-RISC-Core-based-on-Harvard-Architecture-
This project aims to implement a 32-bit 5-stage pipelined High-performance MIPS-based RISC Core based on Harvard Architecture. The MIPS processor was designed using MIPS ISA (Instruction Set Architecture) and divided into three main modules: datapath unit, control unit, and hazard unit. The processor is tested to run two programs: GCD Calculation of two numbers and Factorial Calculation of a number. Programs are written in MIPS assembly code, then converted to machine code. Verilog HDL language is used on ModelSim Simulation tool to verify the functional simulation of the processor and compare between five-stage pipelined MIPS processor and single-cycle MIPS processor regarding performance analysis. Keywords: Pipelined MIPS Processor, Harvard Architecture, MIPS Assembly, Functional Simulation, Datapath, Hazard Unit.
Mostafa-Hassanien/Digital-Design-System
It is responsible for doing some processing using ALU block on Register File stored data to generate byte data then add CRC bits to generate a packet and send it using Serial Communication Protocol UART
Mostafa-Hassanien/FSMD-NIOS-II-SoC-and-ARM-Cortex-M0-SoC
This project aims to compare the performance of Implementing 3x3 Matrix multiplier using three different implementations (FSMD, NIOS II SoC, and ARM Cortex M0 SoC) from three different approaches: functional simulation, timing analysis, and execution time. Then, configuring the three implementations on Cyclone® IV FPGA device.
Mostafa-Hassanien/Simplified-Processor-Module
Mostafa-Hassanien/Single-Cycle-MIPS-Processor-
The aim of this project is to design a 32-bit single-cycle MIPS processor for RISC (Reduced Instruction Set Computer) processor. The MIPS processor was designed using MIPS ISA (Instruction Set Architecture) and divided into two parts: the datapath unit, and the control unit. Verilog HDL language to design hardware modeling is used on ModelSim tool. Keywords: MIPS, RISC, ISA, datapath, Verilog.
Mostafa-Hassanien/Assembly-Game
Mostafa-Hassanien/Restaurant-Management
Mostafa-Hassanien/A-simple-game-application