OmniaMohamed12/Memory-Verification-using-UVM-and-SystemVerilog

Verification of Memory Using Class Based Environment and UVM Environment

Memory-Verification-using-UVM-and-SystemVerilog

This project focuses on The Verification of a single port ram Using Class Based Environment and UVM.

UVM Architecture

Class Based Env

Compilation and Simulation Steps

To compile the design and testbench, use the following command:

vlog pack1.sv top.sv +cover

To simulate and run test with coverage analysis, use the following command:

vsim -batch top -coverage -do "run -all; coverage report -codeAll -cvg -verbose"