Powerhouse28's Stars
TheAlgorithms/Python
All Algorithms implemented in Python
microsoft/ML-For-Beginners
12 weeks, 26 lessons, 52 quizzes, classic Machine Learning for all
mrdbourke/pytorch-deep-learning
Materials for the Learn PyTorch for Deep Learning: Zero to Mastery course.
cocotb/cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
siliconcompiler/siliconcompiler
Modular hardware build system
juanchosaravia/KedditBySteps
Small Reddit Android client developed with Kotlin
PyHDI/Pyverilog
Python-based Hardware Design Processing Toolkit for Verilog HDL
viduraakalanka/HDL-Bits-Solutions
This is a repository containing solutions to the problem statements given in HDL Bits website.
PyHDI/veriloggen
Veriloggen: A Mixed-Paradigm Hardware Construction Framework
abdelazeem201/ASIC-Design-Roadmap
The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.
NVlabs/AutoDMP
fabianfiorotto/quick-query
Do queries against your local databases
Daikon-Sun/Physical-Design-for-Nanometer-ICs
Assignments of Physical Design for Nanometer ICs (Spring 2017, Prof. Yao-Wen Chang)
hughbyrne10/100daysofRTL
100 Days Of RTL is a personal challenge designed to help improve skills and knowledge in digital circuit design. The challenge involves committing to working on RTL based digital designs for 100 consecutive days. The goal is to build a solid foundation of knowledge and experience in the field.
myhdl/site-myhdl
myhdl.org website
Powerhouse28/Project
ENGR 850
dsatizabal/tt03-dsp-4bits-sequential-alu
4-bits sequential ALU for Tiny Tapeout 03