Rohan7Gupta

Rohan7Gupta's Stars

• PacktPublishing/ROS-2-from-Scratch

  ROS 2 from Scratch, published by Packt

  Language:Python2312

• clearpathrobotics/roscon2024-workshop-demystifying-ros2-networking

  ROSCon 2024 Workshop: Demystifying ROS 2 Networking

  11612

• amanh-iitj/avsddac_7nm

  This repository contains the design and implementation of a 10-bit R2R Digital-to-Analog Converter (DAC). The design has been created using FinFET technology and is implemented with the ASAP7nm Process Design Kit (PDK).

  4

• AsahiroKenpachi/asap_7nm_Xschem

  51

• muhammadaldacher/Analog-Design-of-Asynchronous-SAR-ADC

  This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) implemented in 45nm CMOS technology.

  14218

• fayizferosh/soc-design-and-planning-nasscom-vsd

  2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advanced Physical Design using OpenLANE/Sky130)

  Language:Verilog1312

• Rohan7Gupta/pentaRV

  pentaRV consists of a 5 stage pipelined Rv32I core and the project plans to implement a RISC-V based SOC .

  Language:Verilog3

• AngeloJacobo/OpenLANE-Sky130-Physical-Design-Workshop

  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130

  5115

• google/skywater-pdk

  Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

  Language:Python3k395

• nickson-jose/vsdstdcelldesign

  This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedures on how to create a custom LEF file and plugging it into an openlane flow.

  Language:Verilog6341

• efabless/openlane2

  The next generation of OpenLane, rewritten from scratch with a modular architecture

  Language:Python24841

• maazm007/vsdsquadron-mini-internship

  VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.

  Language:C185

• vinayrayapati/rv32i

  Implementation of RISC-V RV32I

  Language:Verilog145

• 7vik-g/16bit-pipelined-RISC-processor-sky130

  Language:Verilog152

• cnlohr/ch32v003fun

  Open source minimal stack for the ch32 line of WCH processors, including the ch32v003, a 10¢ 48 MHz RISC-V Microcontroller - as well as many other chips within the ch32v/x line.

  Language:C1k158

• HanzoutiMehdi/fft_touchgfx_stm32h7

  FFT_TouchGFX_STM32H7

  Language:C72

• eceelango/RISC-V_HDP

  RISC V HDP Training Files

  Language:Verilog4

• cpldcpu/BitNetMCU

  Neural Networks with low bit weights on low end 32 bit microcontrollers such as the CH32V003 RISC-V Microcontroller and others

  Language:C25024

• Qucs/ADMS

  ADMS is a code generator for the Verilog-AMS language

  Language:Perl9431

• Fahad-Habib/RISC-V-Pipelined-Processor-with-CSR

  3-stage RISC-V Pipelined Processor with interrupt CSR support

  Language:SystemVerilog3

• jdah/jdh-8

  An 8-bit minicomputer with a fully custom architecture

  Language:C1.3k91

• habibagamal/RISC-V-Implementation

  This is a Verilog Implementation of RISC-V CPU that implements RV32I and RV16I and supports interrupt handling and some CSR instuctions and registers

  Language:Verilog52

• Devipriya1921/VSDBabySoC_ICC2

  Language:Verilog82

• adam-maj/tiny-gpu

  A minimal GPU design in Verilog to learn how GPUs work from the ground up

  Language:SystemVerilog7.2k547

• riscv-software-src/riscv-isa-sim

  Spike, a RISC-V ISA Simulator

  Language:C2.5k877

• riscv-collab/riscv-gnu-toolchain

  GNU toolchain for RISC-V, including GCC

  Language:C3.6k1.2k

• sifive/elf2hex

  Converts ELF files to HEX files that are suitable for Verilog's readmemh.

  Language:Shell8221

• RobertBaruch/riscv-reboot

  Language:Python426

• RobertBaruch/nmigen-tutorial

  A tutorial for using nmigen

  30934

• YosysHQ/picorv32

  PicoRV32 - A Size-Optimized RISC-V CPU

  Language:Verilog3.2k767