/MIPS-Processor

Implementation of a 32-bit MIPS processor using Verilog HDL with advanced features like a 5-stage pipeline and instruction/data caches.

Primary LanguageVerilog

MIPS Processor

Implementation of a pipelined MIPS processor using Verilog HDL that supports a 32-bit MIPS ISA

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Features

The implemented MIPS processor supports the following features:

  • 32-bit MIPS ISA
  • 5-stage pipeline datapath
  • Instruction and data caches

Getting Started

To get started with this project, follow these steps:

  1. Clone the repository: git clone https://github.com/Roodaki/MIPS-Processor
  2. Install a Verilog simulator, such as Icarus Verilog
  3. Open the desired Verilog file in the simulator and compile it: iverilog -o output.vvp file.v
  4. Run the compiled simulation: vvp output.vvp
  5. View the waveforms using a waveform viewer, such as GTKWave: gtkwave output.vcd

Future Development

Possible areas for improving the implemented MIPS processor and enhancing its capabilities include:

  • Implementing a forwarding unit (to improve performance by reducing stalls)
  • Incorporating a branch prediction unit (for more efficient branch handling)
  • Implementing a hazard detection unit (for better handling of data and control hazards)