Implementation of a pipelined MIPS processor using Verilog HDL that supports a 32-bit MIPS ISA
The implemented MIPS processor supports the following features:
- 32-bit MIPS ISA
- 5-stage pipeline datapath
- Instruction and data caches
To get started with this project, follow these steps:
- Clone the repository:
git clone https://github.com/Roodaki/MIPS-Processor
- Install a Verilog simulator, such as Icarus Verilog
- Open the desired Verilog file in the simulator and compile it:
iverilog -o output.vvp file.v
- Run the compiled simulation:
vvp output.vvp
- View the waveforms using a waveform viewer, such as GTKWave:
gtkwave output.vcd
Possible areas for improving the implemented MIPS processor and enhancing its capabilities include:
- Implementing a forwarding unit (to improve performance by reducing stalls)
- Incorporating a branch prediction unit (for more efficient branch handling)
- Implementing a hazard detection unit (for better handling of data and control hazards)