Roodaki/MIPS-Processor
Implementation of a 32-bit MIPS processor using Verilog HDL with advanced features like a 5-stage pipeline and instruction/data caches.
Verilog
No issues in this repository yet.
Implementation of a 32-bit MIPS processor using Verilog HDL with advanced features like a 5-stage pipeline and instruction/data caches.
Verilog
No issues in this repository yet.