Satvik3799

Satvik3799's Stars

• rclone/rclone

  "rsync for cloud storage" - Google Drive, S3, Dropbox, Backblaze B2, One Drive, Swift, Hubic, Wasabi, Google Cloud Storage, Azure Blob, Azure Files, Yandex Files

  Language:Go48k5685.6k4.3k

• cython/cython

  The most widely used Python to C compiler

  Language:Python9.7k2403.8k1.5k

• Slackadays/Clipboard

  😎🏖️🐬 Your new, 𝙧𝙞𝙙𝙤𝙣𝙠𝙪𝙡𝙞𝙘𝙞𝙤𝙪𝙨𝙡𝙮 smart clipboard manager

  Language:C++4.9k29120149

• openhwgroup/cva6

  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

  Language:Assembly2.3k931.1k706

• darklife/darkriscv

  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

  Language:Verilog2.2k9440292

• pit-ray/win-vind

  You can operate Windows with key bindings like Vim.

  Language:C++2k1620845

• stnolting/neorv32

  :desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

  Language:VHDL1.6k52215234

• dockur/windows-arm

  Windows for ARM in a Docker container.

  Language:Shell1.3k1746120

• Xilinx/Vitis-Tutorials

  Vitis In-Depth Tutorials

  Language:C1.3k53243559

• gpgpu-sim/gpgpu-sim_distribution

  GPGPU-Sim provides a detailed simulation model of contemporary NVIDIA GPUs running CUDA and/or OpenCL workloads. It includes support for features such as TensorCores and CUDA Dynamic Parallelism as well as a performance visualization tool, AerialVisoin, and an integrated energy model, GPUWattch.

  Language:C++1.2k46171519

• alexforencich/verilog-pcie

  Verilog PCI express components

  Language:Verilog1.2k5251310

• geerlingguy/sbc-reviews

  Jeff Geerling's SBC review data - Raspberry Pi, Radxa, Orange Pi, etc.

  660495013

• JulianKemmerer/PipelineC

  A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

  Language:VHDL6112513350

• DiegoPaezA/ESP32-freeRTOS

  Basic Examples of FreeRTOS with ESP32 and ESP-IDF

  Language:C3358276

• arm-university/Introduction-to-Computer-Architecture-Education-Kit

  Gain an understanding of the fundamental topics and concepts of computer architecture including the application of these with modern Arm processors

  Language:HTML2575147

• arm-university/VLSI-Fundamentals-Education-Kit

  Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical implementation of a simplified microprocessor

  Language:HTML2186154

• intel/FPGA-Devcloud

  Get started using Intel® FPGA tools on the Devcloud with tutorials, workshops, advanced courses, and sample projects built specifically for students, researchers, and developers. Visit our official Intel® FPGA Devcloud website:

  Language:C++118193164

• D-curs-D/Inverter-design-and-analysis-using-sky130pdk

  Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools

  Language:Shell1034021

• ecilasun/tinysys

  A tiny system built on a small QMTECH board

  Language:C++96502

• nishthaparashar/Floating-Point-ALU-in-Verilog

  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.

  Language:Verilog781029

• arm-university/A-Beginners-Guide-to-Designing-Embedded-System-Applications-on-Arm-Cortex-M-Microcontrollers

  A 'learn by doing' textbook on building an embedded system

  682015

• psnjk/SimpleCache

  Simple cache design implementation in verilog

  Language:Verilog411014

• arm-university/Operating-Systems-Foundations-with-Linux-on-the-Raspberry-Pi

  A textbook on the introduction to the foundations of modern operating systems with Linux

  37307

• dvanmali/Superscalar_Pipeline_Processor

  Design consists of a 32-bit MIPS superscalar pipeline processor in functional Verilog. Runs a cache based memory system, a branch predictor, and a 2-way superscalar pipeline processor issuing two instructions at a time. Intended for creators Yiming Gan and Dylan Vanmali.

  Language:Verilog13312

• AnoushkaTripathi/My_Very_first_RTLtoGDS-Project

  Language:Verilog7103

• takatz28/FIFO-BIST

  Final project for the class "Application Specific Integrated Circuit Development"

  Language:SystemVerilog7100

• joses-bot/sfal-vsd

  Language:Verilog52

• hangryusprime/BIST

  Language:Verilog4300

• titto-thomas/superscalar

  Superscalar version of IITB pipeline RISC

  Language:VHDL3300

• CSAIL-Arch-Sec/SHD-RISCVRec

  Language:Assembly1201