/AES-128

RTL implementation of the AES algorithm with 128-bit key using Verilog.

Primary LanguageVerilog

AES-128

This project is an RTL-based implementation of AES with a 128-bits key. It uses ten rounds for 128-bit keys. Each round comprises a series of operations as follows:

  • Byte substitution
  • Rows shifting
  • Matrix multiplication
  • Adding with a key specific for each round