Shehab-Naga
ECE Ph.D. student at The Ohio State University | Graduate RA at ElectroScience Lab
ElectroScience Lab @ The Ohio State UniversityColumbus, Ohio, USA
Pinned Repositories
AES-128
RTL implementation of the AES algorithm with 128-bit key using Verilog.
Analog-Mixed-Signal-Simulation-and-Modeling
This is my labs for the AMS simulation and modeling Training of Siemens EDA in Summer 2022, delivered by Dr. Hesham Omran.
ddr5_phy
DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
elevator-controller
VHDL RTL Design, Verification, and FPGA Implementation of an Elevator Controller
Gray-Code-Counter
This project involved designing a digital circuit for a gray code representation on a seven-segment display, then using Quartus Prime and Altera’s FPGA to implement the counter.
Modeling-of-90nm-NMOS-and-PMOS-FETs
Analytical model is developed using Matlab describing the transistor operation for both an N- and P-type MOSFETs.
QPSK-Communication-System-Modeling
A MATLAB implementation for quadrature phase-shift keying communication system.
SnakeGame
This project is done using C++, SFML library, and OOP concepts.
VHDL-Exercises
My work for the laboratory exercises provided by intel FPGAcademy (Digital Logic) during my internship at PyramidTech in Summer 2022.
washing-machine-controller
Verilog HDL implementation and verification of a controller unit of washing machine.
Shehab-Naga's Repositories
Shehab-Naga/ddr5_phy
DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
Shehab-Naga/Analog-Mixed-Signal-Simulation-and-Modeling
This is my labs for the AMS simulation and modeling Training of Siemens EDA in Summer 2022, delivered by Dr. Hesham Omran.
Shehab-Naga/Modeling-of-90nm-NMOS-and-PMOS-FETs
Analytical model is developed using Matlab describing the transistor operation for both an N- and P-type MOSFETs.
Shehab-Naga/QPSK-Communication-System-Modeling
A MATLAB implementation for quadrature phase-shift keying communication system.
Shehab-Naga/Gray-Code-Counter
This project involved designing a digital circuit for a gray code representation on a seven-segment display, then using Quartus Prime and Altera’s FPGA to implement the counter.
Shehab-Naga/VHDL-Exercises
My work for the laboratory exercises provided by intel FPGAcademy (Digital Logic) during my internship at PyramidTech in Summer 2022.
Shehab-Naga/AES-128
RTL implementation of the AES algorithm with 128-bit key using Verilog.
Shehab-Naga/elevator-controller
VHDL RTL Design, Verification, and FPGA Implementation of an Elevator Controller
Shehab-Naga/Matlab-Study-Notes
Shehab-Naga/SnakeGame
This project is done using C++, SFML library, and OOP concepts.
Shehab-Naga/washing-machine-controller
Verilog HDL implementation and verification of a controller unit of washing machine.
Shehab-Naga/semiconductorsCalculator
Using MATLAB GUI, this project is a calculators for some important semiconductors' parameters as the number of electrons, holes and the fermi level for some materials depending on the temperature and doping.
Shehab-Naga/tree-cli
🌴List contents of directories in tree-like format.