Shreesh-Kulkarni
SoC Design @intel | LFX'24 @openhwgroup | Open Source Dev @riscv and @riscv-software-src | Aspiring Computer Architect| EEE NITK'24
@intelBangalore,Karnataka,India
Shreesh-Kulkarni's Stars
tenstorrent/riscv_arch_tests
Self checking RISC-V directed tests
openhwgroup/cvw-arch-verif
The purpose of the repo is to support CORE-V Wally architectural verification
rsnikhil/Learn_Bluespec_and_RISCV_Design
Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
riscv/riscv-double-trap
RISC-V Double Trap Fast-Track Extension
riscv/riscv-crypto
RISC-V cryptography extensions standardisation work.
riscv-non-isa/riscv-trace-spec
RISC-V Processor Trace Specification
riscv/learn
Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.
riscv/riscv-cheri
This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
hpcgarage/spatter
Benchmark for measuring the performance of sparse and irregular memory access.
rsnikhil/Bluespec_BSV_Tutorial
Bluespec BSV HLHDL tutorial
riscv/sail-riscv
Sail RISC-V model
rems-project/sail
Sail architecture definition language
riscv-software-src/riscv-isac
YosysHQ/nextpnr
nextpnr portable FPGA place and route tool
pulp-platform/pulp_cluster
The multi-core cluster of a PULP system.
NiharGowdaS/MP_EE_24-V
darklife/darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
zeroasiccorp/logik
A configurable RTL to bitstream FPGA toolchain
openhwgroup/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
openhwgroup/cv-hpdcache
RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
riscvarchive/riscv-code-size-reduction
schoeberl/chisel-book
Digital Design with Chisel
IntelLabs/riscv-vector
Vector Acceleration IP core for RISC-V*
grayresearch/CX
Proposed RISC-V Composable Custom Extensions Specification
YosysHQ/oss-cad-suite-build
Multi-platform nightly builds of open source digital design and verification tools
eembc/coremark
CoreMark® is an industry-standard benchmark that measures the performance of central processing units (CPU) and embedded microcrontrollers (MCU).
riscv-verification/riscvISACOV
SystemVerilog Functional Coverage for RISC-V ISA
riscv-software-src/riscv-ctg
riscv-software-src/riscof
riscv/riscv-debug-spec
Working Draft of the RISC-V Debug Specification Standard