SweetWeeds

SweetWeeds's Stars

• ufrisk/pcileech

  Direct Memory Access (DMA) Attack Software

  Language:C5k148284731

• B-Lang-org/bsc

  Bluespec Compiler (BSC)

  Language:Haskell95249313146

• ufrisk/pcileech-fpga

  FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software

  Language:Verilog87646171193

• ucb-bar/gemmini

  Berkeley's Spatial Array Generator

  Language:Scala80730184168

• projf/projf-explore

  Project F brings FPGAs to life with exciting open-source designs you can build on.

  Language:SystemVerilog584383252

• pulp-platform/common_cells

  Common SystemVerilog components

  Language:SystemVerilog5081957145

• accellera-official/systemc

  SystemC Reference Implementation

  Language:C++4844461152

• mariusmm/RISC-V-TLM

  RISC-V SystemC-TLM simulator

  Language:C275191472

• alexforencich/verilog-cam

  Verilog Content Addressable Memory Module

  Language:Verilog10112547

• Algolzw/EBSR

  Pytorch code for "EBSR: Feature Enhanced Burst Super-Resolution with Deformable Alignment", CVPRW 2021, 1st NTIRE (real data track).

  Language:Python9451411

• vortexgpgpu/skybox

  Vortex Graphics

  Language:Verilog594411

• freecores/sparc64soc

  OpenSPARC-based SoC

  Language:Verilog589030

• freecores/dma_ahb

  AHB DMA 32 / 64 bits

  Language:Verilog506121

• freecores/verilog_cordic_core

  configurable cordic core in verilog

  Language:Verilog462014

• freecores/xge_mac

  Ethernet 10GE MAC

  Language:Verilog447024

• RSPwFPGAs/qemu-hdl-cosim

  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs

  Language:Verilog397116

• freecores/jtag

  JTAG Test Access Port (TAP)

  Language:Verilog303112

• freecores/ddr3_sdram

  DDR3 SDRAM controller

  Language:Verilog1812

• freecores/y80e

  Y80e - Z80/Z180 compatible processor extended by eZ80 instructions

  Language:Verilog185

• freecores/zet86

  Zet - The x86 (IA-32) open implementation

  Language:C18403

• freecores/ps2

  PS2 interface

  Language:Verilog17307

• freecores/double_fpu

  double_fpu_verilog

  Language:Verilog154

• freecores/mmu180

  MMU for Z80 and eZ80

  Language:Verilog15503

• freecores/pci

  PCI bridge

  Language:Verilog149

• freecores/wdsp

  DSP WishBone Compatible Cores

  Language:Verilog13304

• freecores/bluespec-h264

  Bluespec H.264 Decoder

  Language:Bluespec11405

• freecores/pipelined_fft_64

  Pipelined FFT/IFFT 64 points processor

  Language:Verilog11205

• olgirard/opengfx430

  The openGFX430 is a synthesizable Graphic controller written in Verilog and tailored for the openMSP430 core.

  Language:Verilog7302

• freecores/noc

  NoC(Network-on-Chip) Simulator

  Language:C++4202

• webserver3315/Graduate_Project

  MNIST with C++ and Verilator, using SystemVerilog Interpreting FP32 FPU and MAC,

  Language:C310