Tiarles/twd_asic_processor
This project was carried out for the discipline Integrating Digital Systems Project. It is a processor that does the non-orthogonal transform of haar into an input signal.
VHDL
No issues in this repository yet.
This project was carried out for the discipline Integrating Digital Systems Project. It is a processor that does the non-orthogonal transform of haar into an input signal.
VHDL
No issues in this repository yet.