Tiarles/twd_asic_processor
This project was carried out for the discipline Integrating Digital Systems Project. It is a processor that does the non-orthogonal transform of haar into an input signal.
VHDL
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This project was carried out for the discipline Integrating Digital Systems Project. It is a processor that does the non-orthogonal transform of haar into an input signal.
VHDL
No one’s star this repository yet.