TimRudy

angular-tuenkd-custom-input

Created with StackBlitz ⚡️

electric-cpu

Home-designed CPU, and a documented process to build it

events-app-external

events-app-internal

ice-chips-verilog

IceChips is a library of all common discrete logic devices in Verilog

icestudio

:snowflake: Visual editor for open FPGA boards

open-fpga-verilog-tutorial

Aprender a diseñar sistemas digitales sintetizables en FPGAs usando SOLO herramientas libres #verilog #icestorm #lattice #Linux

saturn-datepicker

Angular Material Datepicker with range selection

uart-verilog

A simple 8 bit UART implementation in Verilog, with tests and timing diagrams

yosys

Yosys Open SYnthesis Suite

TimRudy/ice-chips-verilog

IceChips is a library of all common discrete logic devices in Verilog

TimRudy/uart-verilog

A simple 8 bit UART implementation in Verilog, with tests and timing diagrams

TimRudy/yosys

Yosys Open SYnthesis Suite

TimRudy/electric-cpu

Home-designed CPU, and a documented process to build it

TimRudy/icestudio

:snowflake: Visual editor for open FPGA boards

TimRudy/open-fpga-verilog-tutorial

Aprender a diseñar sistemas digitales sintetizables en FPGAs usando SOLO herramientas libres #verilog #icestorm #lattice #Linux

TimRudy/angular-tuenkd-custom-input

Created with StackBlitz ⚡️

TimRudy/events-app-external

TimRudy/events-app-internal

TimRudy/saturn-datepicker

Angular Material Datepicker with range selection

TimRudy/TimRudy.github.io

Personal Website