Tsriram95

Tsriram95's Stars

• google-research/circuit_training

  Language:Python1.1k176

• vijaymarupudi/nvim-fzf-commands

  Assorted commands using nvim-fzf

  Language:Lua453

• vijaymarupudi/nvim-fzf

  A Lua API for using fzf in neovim.

  Language:Lua33612

• neovim/neovim

  Vim-fork focused on extensibility and usability

  Language:Vim Script82.3k5.6k

• asinghani/open-eda-course

  Language:Jupyter Notebook517

• enics-labs/kahoot-merger

  A python script for parsing Kahoot! result excels.

  Language:Python1

• abdelazeem201/Resume

  A one-page, one column resume template in LaTeX that caters particularly to an undergraduate ECE/CSE student.

  Language:TeX2

• abdelazeem201/ASIC-Design-Roadmap

  The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.

  Language:Verilog23330

• abdelazeem201/Introduction-to-System-on-Chip-Design-Online-Course

  To develop Arm Cortex-M0 based SoCs, from creating high-level functional specifications to design, implementation and testing on FPGA platforms using standard hardware description and software programming languages

  Language:Verilog186

• calvint/AlgorithmsOneProblems

  Homeworks from Algorithms 1

  Language:Python12354

• agucova/awesome-esp

  📶 A curated list of awesome ESP8266/32 projects and code

  1.1k68

• JulianKemmerer/PipelineC

  A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

  Language:Python58847

• streamlit/streamlit-app-action

  Simple GitHub Action workflows for validating a Streamlit app

  Language:Python122

• troyguo/awesome-dv

  Awesome ASIC design verification

  24762

• HDLForBeginners/Examples

  Language:Verilog7425

• pengwubj/hw_interview_questions

  A collection of commonly asked RTL design interview questions

  Language:SystemVerilog2015

• fpgadeveloper/fpga-drive-aximm-pcie

  Example designs for FPGA Drive FMC

  Language:Tcl21299

• muneebullashariff/best_coding_practices

  Describes the best coding practices and guidelines

  Language:Vim Script1016

• mbits-mirafra/spi_avip

  Language:SystemVerilog94

• mbits-mirafra/apb_avip

  Language:SystemVerilog148

• mbits-mirafra/UVMCourse

  Structured UVM Course

  Language:SystemVerilog3212

• mbits-mirafra/SystemVerilogCourse

  This is a detailed SystemVerilog course

  Language:SystemVerilog6931

• raysalemi/uvmprimer

  Contains the code examples from The UVM Primer Book sorted by chapters.

  Language:SystemVerilog475203

• ddvca/2022-bishkek

  Language:SystemVerilog46

• raulbehl/100DaysOfRTL

  100 Days of RTL

  Language:SystemVerilog32796

• chipsalliance/yosys-f4pga-plugins

  Plugins for Yosys developed as part of the F4PGA project.

  Language:Verilog8246

• siliconcompiler/siliconcompiler

  Modular hardware build system

  Language:Python85184

• The-OpenROAD-Project/OpenROAD-flow-scripts

  OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

  Language:Verilog322280

• The-OpenROAD-Project/OpenLane

  OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

  Language:Python1.3k372

• The-OpenROAD-Project/OpenROAD

  OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

  Language:Verilog1.5k536