acomodi

acomodi's Stars

• verilog-to-routing/vtr-verilog-to-routing

  Verilog to Routing -- Open Source CAD Flow for FPGA Research

  Language:C++1k671k397

• olofk/edalize

  An abstraction library for interfacing EDA tools

  Language:Python65233166194

• os-fpga/1st-CLaaS

  Framework for developing and deploying FPGA logic in the cloud as a microservice for web and cloud applications

  Language:C198161942

• hendrikmuhs/ccache-action

  github action to speedup building using ccache

  Language:TypeScript12425554

• chipsalliance/python-fpga-interchange

  Python interface to FPGA interchange format

  Language:Python41153012

• necst/iron

  Image Registration on FPGAs

  Language:C++19601

• chipsalliance/f4pga-xc7-bram-patch

  Tool for updating the contents of BlockRAMs found in Xilinx 7 series bitstreams.

  Language:LLVM1713164

• hzeller/symbiflow-simple-sample

  Using Symbiflow arch defs to get BASYS3 board entertained with logic

  Language:Makefile8331

• SymbiFlow/FPGA-Tool-Performance-Visualization-Library

  FTPVL is a library for simplifying the data collection and visualization process for Symbiflow development.

  Language:Python6393

• SymbiFlow/sphinxcontrib-markdown-symlinks

  Python library to solve markdown cross-reference links when building sphinx documentation

  Language:Python31373