adajani

adajani's Stars

• MazinCE/Veecom

  A Simple Yet Powerful RISC-V Computer

  Language:C11010

• xuluna/smartssd

  Example for Samsung smart ssd

  Language:C++85

• lydiawunan/IronMan

  IronMan+alpha: Graph Neural Network and Reinforcement Learning in High-Level Synthesis

  Language:C++237

• dgschwend/zynqnet

  Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"

  Language:HTML738297

• rejunity/tt05-psg-sn76489

  TinyTapeout submission with the SN76489 Digital Complex Sound Generator (DCSG) programmable sound generator (PSG) chip from Texas Instruments.

  Language:Python527

• alexfru/SmallerC

  Simple C compiler

  Language:C1.4k156

• microsoft/WSL2-Linux-Kernel

  The source for the Linux kernel used in Windows Subsystem for Linux 2 (WSL2)

  Language:C8k1.1k

• Digilent/vivado-boards

  Language:Tcl381211

• stevehoover/LF-Building-a-RISC-V-CPU-Core

  Language:TL-Verilog330178

• projf/projf-explore

  Project F brings FPGAs to life with exciting open-source designs you can build on.

  Language:SystemVerilog56651

• shivanishah269/risc-v-core

  This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

  Language:Verilog6841

• ShawnHymel/introduction-to-fpga

  Language:Verilog15336

• LukeVassallo/tt03-xor-cipher

  Verilog demo for Tiny Tapeout 03

  Language:Tcl41

• DmitryZlobec/yrv-omdazz

  Language:Verilog52

• MoatLab/FEMU

  FEMU: Accurate, Scalable and Extensible NVMe SSD Emulator (FAST'18)

  Language:C417194

• Farbod-Siahkali/Digital-Logical-Designs-Projects

  Digital Logical Designs Course Projects

  Language:Verilog2

• akilm/FPU-IEEE-754

  Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Square Root Operations based on the IEEE-754 standard for floating point numbers

  Language:Verilog389

• ultraembedded/riscv

  RISC-V CPU Core (RV32IM)

  Language:Verilog1.2k225

• ash-olakangal/RISC-V-Processor

  Verilog implementation of multi-stage 32-bit RISC-V processor

  Language:Verilog6623

• darklife/darkriscv

  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

  Language:Verilog2.1k281

• devAmoghS/Python-Interview-Problems-for-Practice

  120+ Common code and interview problems solved in Python **(it's GROWING...)** Give a Star 🌟If it helps you. Please go through the README.md before starting.

  Language:Jupyter Notebook977153

• rockchip-linux/kernel

  BSP kernel source

  Language:C9171.1k

• hydrabus/hydrafw

  HydraBus HydraFW official firmware for open source multi-tool for anyone interested in learning/developping/debugging/hacking/Penetration Testing for basic or advanced embedded hardware

  Language:C36292

• riscv-collab/riscv-gnu-toolchain

  GNU toolchain for RISC-V, including GCC

  Language:C3.4k1.1k

• Marco-Winzker/NN_RGB_FPGA

  FPGA Design of a Neural Network for Color Detection

  Language:VHDL6828

• davepoo/6502Emulator

  Learning how a CPU works by emulating one

  Language:C++49988

• Shark-ML/Shark

  The Shark Machine Leaning Library. See more:

  Language:C++505131

• jMetal/jMetalCpp

  A C++ version of jMetal, a Java framework aimed at multi-objective optimization with metaheuristics.

  Language:C++6434