aitesam961

aitesam961's Stars

• opencv/opencv

  Open Source Computer Vision Library

  Language:C++78.9k2.7k10.8k55.8k

• BrunoLevy/learn-fpga

  Learning FPGA, yosys, nextpnr, and RISC-V

  Language:C++2.6k8474245

• IanHarvey/bluepy

  Python interface to Bluetooth LE on Linux

  Language:C1.6k101397490

• stnolting/neorv32

  :desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

  Language:VHDL1.6k50201224

• AfterEarthLTD/Solder-Reflow-Plate

  PCB based SMD reflow plates

  Language:C++1.4k5637243

• ultraembedded/riscv

  RISC-V CPU Core (RV32IM)

  Language:Verilog1.2k5118233

• jankae/LibreVNA

  100kHz to 6GHz 2 port USB based VNA

  Language:C++1.1k85159209

• T-head-Semi/openc910

  OpenXuantie - OpenC910 Core

  Language:Verilog1.1k4524286

• riscv/riscv-v-spec

  Working draft of the proposed RISC-V V vector extension

  Language:Assembly962131704273

• ultraembedded/biriscv

  32-bit Superscalar RISC-V CPU

  Language:Verilog8592925146

• syntacore/scr1

  SCR1 is a high-quality open-source RISC-V MCU core in Verilog

  Language:SystemVerilog8585156275

• eugene-tarassov/vivado-risc-v

  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

  Language:Tcl83537206190

• riscv/riscv-opcodes

  RISC-V Opcodes

  Language:Python6918566300

• mnurzia/rv

  32-bit RISC-V CPU in ~800 lines of C89

  Language:C60612427

• lowRISC/style-guides

  lowRISC Style Guides

  3676934123

• IntelLabs/riscv-vector

  Vector Acceleration IP core for RISC-V*

  Language:Scala1466122

• kuopinghsu/srv32

  Simple 3-stage pipeline RISC-V processor

  Language:C1331526

• aeonSolutions/AeonLabs-AI-Volvo-MKII-Open-Hardware

  Volvo MKII Open Hardware

  13113122

• tomverbeure/rt

  A Full Hardware Real-Time Ray-Tracer

  Language:Verilog904113

• aignacio/nox

  RISC-V Nox core

  Language:C60716

• tomverbeure/mr1

  MR1 formally verified RISC-V CPU

  Language:Scala51205

• avl-bsuir/rv64x-base

  Open source GPU extension for RISC-V

  Language:Dockerfile44305

• ksco/riscv-vector-tests

  Unit tests generator for RVV 1.0

  Language:Go4141815

• aswaterman/trainwreck

  Original RISC-V 1.0 implementation. Not supported.

  Language:Verilog405214

• wyvernSemi/riscV

  Open source ISS and logic RISC-V 32 bit project

  Language:C++398113

• brucehoult/rvv_example

  Simple demonstration of using the RISC-V Vector extension

  Language:Assembly36409

• gsauthof/riscv

  RISC-V vector and other assembly code examples

  Language:Assembly254212

• byuccl/fiate

  Fault Injection Automatic Test Equipment

  Language:VHDL131004

• hushenwei2000/rvv-atg

  RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Compliance test).

  Language:Python12276

• mikeakohn/riscv_fpga

  Implementation of a RISC-V CPU in Verilog.

  Language:Verilog11302