aitesam961
Electrical Engineer with Interests in Embedded Systems, RISCV, FPGAs, Hardware Design & IoT.
aitesam961.github.ioEarth
aitesam961's Stars
opencv/opencv
Open Source Computer Vision Library
BrunoLevy/learn-fpga
Learning FPGA, yosys, nextpnr, and RISC-V
IanHarvey/bluepy
Python interface to Bluetooth LE on Linux
stnolting/neorv32
:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
AfterEarthLTD/Solder-Reflow-Plate
PCB based SMD reflow plates
ultraembedded/riscv
RISC-V CPU Core (RV32IM)
jankae/LibreVNA
100kHz to 6GHz 2 port USB based VNA
T-head-Semi/openc910
OpenXuantie - OpenC910 Core
riscv/riscv-v-spec
Working draft of the proposed RISC-V V vector extension
ultraembedded/biriscv
32-bit Superscalar RISC-V CPU
syntacore/scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
eugene-tarassov/vivado-risc-v
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
riscv/riscv-opcodes
RISC-V Opcodes
mnurzia/rv
32-bit RISC-V CPU in ~800 lines of C89
lowRISC/style-guides
lowRISC Style Guides
IntelLabs/riscv-vector
Vector Acceleration IP core for RISC-V*
kuopinghsu/srv32
Simple 3-stage pipeline RISC-V processor
aeonSolutions/AeonLabs-AI-Volvo-MKII-Open-Hardware
Volvo MKII Open Hardware
tomverbeure/rt
A Full Hardware Real-Time Ray-Tracer
aignacio/nox
RISC-V Nox core
tomverbeure/mr1
MR1 formally verified RISC-V CPU
avl-bsuir/rv64x-base
Open source GPU extension for RISC-V
ksco/riscv-vector-tests
Unit tests generator for RVV 1.0
aswaterman/trainwreck
Original RISC-V 1.0 implementation. Not supported.
wyvernSemi/riscV
Open source ISS and logic RISC-V 32 bit project
brucehoult/rvv_example
Simple demonstration of using the RISC-V Vector extension
gsauthof/riscv
RISC-V vector and other assembly code examples
byuccl/fiate
Fault Injection Automatic Test Equipment
hushenwei2000/rvv-atg
RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Compliance test).
mikeakohn/riscv_fpga
Implementation of a RISC-V CPU in Verilog.