andreaskurth

awesome-open-hardware-verification

A List of Free and Open Source Hardware Verification Tools and Frameworks

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

BF-FFT-Demo

Graphical demo application for the FFT algorithm on an ADSP-BF532

core-v-docs

Documentation for the OpenHW Group's set of CORE-V RISC-V cores

docker-rust-centos

Docker Image for Rust on CentOS

memora-rs

Memora: Build Artifact Cache for Git Repositories

ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

opentitan

OpenTitan: Open source silicon root of trust

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

hero

Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.

andreaskurth/memora-rs

Memora: Build Artifact Cache for Git Repositories

andreaskurth/docker-rust-centos

Docker Image for Rust on CentOS

andreaskurth/awesome-open-hardware-verification

A List of Free and Open Source Hardware Verification Tools and Frameworks

andreaskurth/axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

andreaskurth/BF-FFT-Demo

Graphical demo application for the FFT algorithm on an ADSP-BF532

andreaskurth/core-v-docs

Documentation for the OpenHW Group's set of CORE-V RISC-V cores

andreaskurth/cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

andreaskurth/docker-rust-ubuntu

Docker Image for Rust on Ubuntu

andreaskurth/gh-workflow-test

andreaskurth/ibex

Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

andreaskurth/ibex-demo-system

A demo system for Ibex including debug support and some peripherals

andreaskurth/lowrisc-fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

andreaskurth/moore

HDL compiler based on LLHD

andreaskurth/morty

A SystemVerilog source file pickler.

andreaskurth/noxim

Network on Chip Simulator

andreaskurth/opentitan

OpenTitan: Open source silicon root of trust

andreaskurth/ot-sca

Side-channel analysis setup for OpenTitan

andreaskurth/pspin

PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing

andreaskurth/pulp-configs

Contains JSON description of pulp configurations

andreaskurth/pulp-rt

andreaskurth/pulp-sdk

andreaskurth/pulp-tools

andreaskurth/riscv-dbg

RISC-V Debug Support for our PULP RISC-V Cores

andreaskurth/slm_conv

Convert loader files to SLM files for RTL simulation

andreaskurth/SpinalHDL

SpinalHDL core

andreaskurth/two-tree-demo