andreaskurth

andreaskurth's Stars

• torvalds/linux

  Linux kernel source tree

  Language:C180k7.9k053.4k

• fish-shell/fish-shell

  The user-friendly command line shell.

  Language:Rust25.8k2847.2k1.9k

• ycm-core/YouCompleteMe

  A code-completion engine for Vim

  Language:Python25.4k5583.2k2.8k

• abseil/abseil-cpp

  Abseil Common Libraries (C++)

  Language:C++14.8k5898762.6k

• evcxr/evcxr

  Language:Rust5.5k55254217

• google/bloaty

  Bloaty: a size profiler for binaries

  Language:C++4.7k80166344

• jesseduffield/horcrux

  Split your file into encrypted fragments so that you don't need to remember a passcode

  Language:Go4.6k2823122

• ekzhang/rustpad

  Efficient and minimal collaborative code editor, self-hosted, no database required

  Language:Rust3.4k2854148

• google/OpenSK

  OpenSK is an open-source implementation for security keys written in Rust that supports both FIDO U2F and FIDO2 standards.

  Language:Rust3k88192289

• lowRISC/opentitan

  OpenTitan: Open source silicon root of trust

  Language:SystemVerilog2.5k1056.7k754

• tpope/vim-eunuch

  eunuch.vim: Helpers for UNIX

  Language:Vim Script1.8k237874

• emk/rust-musl-builder

  Docker images for compiling static Rust binaries using musl-libc and musl-gcc, with static versions of useful C libraries. Supports openssl and diesel crates.

  Language:Dockerfile1.5k22100193

• lowRISC/ibex

  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

  Language:SystemVerilog1.3k96834523

• The-OpenROAD-Project/OpenLane

  OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

  Language:Python1.3k59948370

• trabucayre/openFPGALoader

  Universal utility for programming FPGA

  Language:C++1.2k37233252

• plotly/plotly.rs

  Plotly for Rust

  Language:Rust1.1k30103104

• newaetech/chipwhisperer

  ChipWhisperer - the complete open-source toolchain for side-channel power analysis and glitching attacks

  Language:C1.1k62354280

• pulp-platform/axi

  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  Language:SystemVerilog1.1k39119256

• spcl/dace

  DaCe - Data Centric Parallel Programming

  Language:Python49117348125

• memfault/interrupt

  A community for embedded software makers.

  Language:C4613517131

• pulp-platform/ara

  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

  Language:C35622180126

• xdslproject/xdsl

  A Python Compiler Design Toolkit

  Language:Python2551942868

• timothyandrew/gh-stack

  Manage PR stacks/chains on Github

  Language:Rust1522415

• spcl/pspin

  PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing

  Language:SystemVerilog9610716

• pulp-platform/hero

  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.

  Language:SystemVerilog9310024

• sgherbst/svinst

  Determines the modules declared and instantiated in a SystemVerilog file

  Language:Rust39565

• lowRISC/ot-sca

  Side-channel analysis setup for OpenTitan

  Language:Jupyter Notebook27158426

• GregAC/rrs

  Rust RISC-V Simulator

  Language:Rust23108

• newaetech/sonata-pcb

  Design files and associated documentation for Sonata PCB, part of the Sunburst Project

  Language:ANTLR125192

• lowRISC/synfi

  OpenTitan FI formal verification framework

  Language:Python102216