/my-verilog-examples

A place to keep my synthesizable verilog examples.

Primary LanguageVerilogMIT LicenseMIT

MY VERILOG EXAMPLES

Tag Latest codeclimate Issue Count MIT License jeffdecola.com

A place to keep my synthesizable verilog examples.

Table of Contents

Documentation and Reference

OVERVIEW

Each example uses iverilog to simulate and GTKWave to view the waveform. I also used Xilinx Vivado to synthesize and program these verilog examples on a Digilent ARTY-S7 FPGA development board.

I declare my ports as follows because that's what the synthesis tools want. Who am I to argue.

    module NAME (
        input             a,     // Input A
        input       [7:0] b,     // Input B
        output reg  [3:0] y);    // Output Y

Also, I would stay away from asynchronous design. It can have problems when you synthesize to an FPGA.

    // DO THIS
    always @(posedge clk) begin
        if (~reset) begin
            ...

    // NOT THIS
    always @(posedge clk or negedge reset) begin

Each example has the following 4 files,

  • *.v - The verilog code files(s)
  • *.vh - A header file listing the included verilog files
  • *_tb.v - The verilog testbench code
  • *_tb.tv - Test vectors used with the testbench

The artifacts created are,

  • *_tb.vvp - The verilog compiled code to be used by the simulator
  • *_tb.vcd - The dump of the waveform data
  • *_tb.gtkw - The GTKWave saved waveform

Where the testbench structure is,

testbench-structure.jpg

BASIC CODE

COMBINATIONAL LOGIC

FPGA DEVELOPMENT BOARDS

  • BUTTONS

    • buttons

      A few different ways to use buttons on a FPGA development board.

SEQUENTIAL LOGIC

SYSTEMS