annngineer
ASIC&FPGA design using VHDL/Verilog/SystemVerilog. Admire Python, smitten with DSP (Digital Signal Processing)
annngineer's Stars
nandland/spi-master
SPI Master for FPGA - VHDL and Verilog
theicfire/makefiletutorial
Learn make by example
personal-army-of-4o/nyanMigen
nyanMigen: pretty face for nMigen (https://github.com/nmigen/nmigen)
mciepluc/cocotb-coverage
Functional Coverage and Constrained Randomization Extensions for Cocotb
antmicro/usb-test-suite-build
Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
swaroopch/byte-of-python
Beginners book on Python - start here if you don't know programming
YosysHQ/yosys
Yosys Open SYnthesis Suite
cocotb/cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
dcblack/ModernSystemC
Example code for Modern SystemC using Modern C++
andres-mancera/ethernet_10ge_mac_SV_tb
SystemVerilog testbench for an Ethernet 10GE MAC core