Designed and implemented a six-staged Pipelined architecture of a multicycle RISC processor using VHDL as part of EE309 Autumn 2017. The architecture was augmented with hazard mitigation techniques and data forwarding.
arunabh98/microprocessor-project
Multicycle and pipeline implementations for a RISC architecture in VHDL - EE309 Autumn 2017, IIT Bombay
VHDL