basberg

basberg's Stars

• astral-sh/ruff

  An extremely fast Python linter and code formatter, written in Rust.

  Language:Rust34.1k845.8k1.1k

• o2sh/onefetch

  Command-line Git information tool

  Language:Rust10.6k41320284

• YosysHQ/yosys

  Yosys Open SYnthesis Suite

  Language:C++3.6k1371.8k893

• enjoy-digital/litex

  Build your hardware, easily!

  Language:C3.1k97835577

• ghdl/ghdl

  VHDL 2008/93/87 simulator

  Language:VHDL2.4k1002.2k372

• Chick2D/neofetch-themes

  Neofetch configs put into a convinient repository

  Language:Shell1.4k1318140

• olofk/fusesoc

  Package manager and build abstraction tool for FPGA/ASIC development

  Language:Python1.2k65393253

• VUnit/vunit

  VUnit is a unit testing framework for VHDL/SystemVerilog

  Language:VHDL75651624267

• gtkwave/gtkwave

  GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.

  Language:C67920233121

• olofk/edalize

  An abstraction library for interfacing EDA tools

  Language:Python65133166194

• UVVM/UVVM

  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/

  Language:VHDL3805520395

• ghdl/ghdl-yosys-plugin

  VHDL synthesis (based on ghdl)

  Language:VHDL3134014633

• SystemRDL/systemrdl-compiler

  SystemRDL 2.0 language compiler front-end

  Language:C++2412616669

• bozokopic/opcut

  Cutting stock problem optimizer

  Language:TypeScript152152341

• hdl/bazel_rules_hdl

  Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)

  Language:Starlark122178545

• open-fpga/core-template

  A template for getting started with FPGA core development

  Language:Verilog1128016

• spacemen3/PDP-1

  Language:Verilog111804

• SystemRDL/PeakRDL

  Control and status register code generator toolchain

  Language:Python108124025

• halfmanhalftaco/fpga-docker

  Tools for running FPGA vendor toolchains with Docker

  Language:Makefile734814

• CollapseLabs/gardening-for-engineers

  A starting point for understanding how to grow vegetables at home

  Language:Python40104

• hdl-registers/hdl-registers

  An open-source HDL register code generator fast enough to run in real time.

  Language:Python384335

• VUnit/vunit_action

  VUnit GitHub action

  Language:VHDL15423

• HDLMake/hdl-make

  Tool for generating multi-purpose makefiles for FPGA projects (clone of hdlmake from CERN)

  Language:Python14209