SyntaxError: invalid syntax error in riscv_instr_pkg.py

[Jstar49]

zhu@zhu-virtual-machine:~/jxx/uvm/riscv-dv$ python3 run.py --simulator=pyflow --test riscv_arithmetic_basic_test --steps gen
Tue, 07 Jun 2022 14:15:43 INFO     Creating output directory: out_2022-06-07
Tue, 07 Jun 2022 14:15:43 INFO     Processing regression test list : /home/zhu/jxx/uvm/riscv-dv/target/rv32imc/testlist.yaml, test: riscv_arithmetic_basic_test
Tue, 07 Jun 2022 14:15:43 INFO     Processing regression test list : /home/zhu/jxx/uvm/riscv-dv/yaml/base_testlist.yaml, test: riscv_arithmetic_basic_test
Tue, 07 Jun 2022 14:15:43 INFO     Found matched tests: riscv_arithmetic_basic_test, iterations:2
Tue, 07 Jun 2022 14:15:43 INFO     Processing simulator setup file : /home/zhu/jxx/uvm/riscv-dv/yaml/simulator.yaml
Tue, 07 Jun 2022 14:15:43 INFO     Found matching simulator: pyflow
Tue, 07 Jun 2022 14:15:43 INFO     Building RISC-V instruction generator
Tue, 07 Jun 2022 14:15:43 INFO     Running RISC-V instruction generator
Tue, 07 Jun 2022 14:15:43 INFO     Generating 2 riscv_arithmetic_basic_test
Tue, 07 Jun 2022 14:15:43 INFO     Running riscv_arithmetic_basic_test with 1 batches
Tue, 07 Jun 2022 14:15:43 INFO     Running riscv_arithmetic_basic_test, batch 1/1, test_cnt:2
Tue, 07 Jun 2022 14:15:44 INFO     Traceback (most recent call last):
  File "/home/zhu/jxx/uvm/riscv-dv/pygen/pygen_src/test/riscv_instr_base_test.py", line 20, in <module>
    from pygen_src.riscv_instr_pkg import *
  File "pygen/pygen_src/riscv_instr_pkg.py", line 1183
    rlb = 1b1
           ^
SyntaxError: invalid syntax

Tue, 07 Jun 2022 14:15:44 ERROR    ERROR return code: True/1, cmd: python3 /home/zhu/jxx/uvm/riscv-dv/pygen/pygen_src/test/riscv_instr_base_test.py --num_of_tests=2 --start_idx=0 --asm_file_name=out_2022-06-07/asm_test/riscv_arithmetic_basic_test --log_file_name=out_2022-06-07/sim_riscv_arithmetic_basic_test_0.log  --target=rv32imc  --gen_test=riscv_instr_base_test  --seed=844377794 --instr_cnt=10000 --num_of_sub_program=0 --directed_instr_0=riscv_int_numeric_corner_stream,4 --no_fence=1 --no_data_page=1 --no_branch_jump=1 --boot_mode=m --no_csr_instr=1

---

class mseccfg_reg_t in pygen/pygen_src/riscv_instr_pkg.py :

# ePMP machine security configuration
class mseccfg_reg_t(IntEnum):
    rlb = 1b1
    mmwp = 1b0
    mml = 1b0

this will lead to errors when I run.
these var look likes some binary variable, so I think is it shoud be like this?:

# ePMP machine security configuration
class mseccfg_reg_t(IntEnum):
    rlb = 0b1
    mmwp = 0b0
    mml = 0b0

There are no more mistakes after I modify it

[aneels3]

Hi @Jstar49
Thanks for bringing up the issue.
This was introduced by a previous PR and is being fixed in #866