chipvn98

chipvn98's Stars

• dxzenith/Plume-Network-Bot

  This script can Check in daily on Plume Network website for you !!

  Language:Shell3220

• WangXuan95/Xilinx-FPGA-PCIe-XDMA-Tutorial

  Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核

  Language:Batchfile41885

• adki/AMBA_AXI_AHB_APB

  AMBA bus lecture material

  Language:Verilog366125

• pulp-platform/axi

  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  Language:SystemVerilog1.1k256

• adam-maj/tiny-gpu

  A minimal GPU design in Verilog to learn how GPUs work from the ground up

  Language:SystemVerilog7k520

• cliffordwolf/SimpleVOut

  A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals

  Language:Verilog22832

• enjoy-digital/litex

  Build your hardware, easily!

  Language:C2.9k556

• riscv/riscv-fast-interrupt

  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)

  Language:Makefile23849

• Summer-Summer/ComputerArchitectureLab

  This repository is used to release the Labs of Computer Architecture Course from USTC

  Language:Verilog3514

• defparam/PCI2Nano-RTL

  An open source FPGA PCI core & 8250-Compatible PCI UART core

  Language:Verilog385

• ultraembedded/core_usb_fs_phy

  USB Full Speed PHY

  Language:Verilog386

• tomtor/HDL-deflate

  FPGA implementation of deflate (de)compress RFC 1950/1951

  Language:Verilog556

• m-labs/tdc-core

  A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs

  Language:Verilog5627

• ultraembedded/core_soc

  Basic Peripheral SoC (SPI, GPIO, Timer, UART)

  Language:Verilog5811

• WalkerLau/DetectHumanFaces

  Real time face detection based on Arm Cortex-M3 DesignStart and FPGA

  Language:Verilog18458

• dpretet/async_fifo

  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

  Language:Verilog24475

• stffrdhrn/sdram-controller

  Verilog SDRAM memory controller

  Language:Verilog29993

• alexforencich/verilog-ethernet

  Verilog Ethernet components for FPGA implementation

  Language:Verilog2.2k685

• YosysHQ/picorv32

  PicoRV32 - A Size-Optimized RISC-V CPU

  Language:Verilog3.1k748

• ultraembedded/cores

  Various HDL (Verilog) IP Cores

  Language:Verilog686209

• ultraembedded/biriscv

  32-bit Superscalar RISC-V CPU

  Language:Verilog844146

• dawsonjon/fpu

  synthesiseable ieee 754 floating point library in verilog

  Language:Verilog519141

• ZipCPU/wbuart32

  A simple, basic, formally verified UART controller

  Language:Verilog27547

• hell03end/verilog-uart

  Simple 8-bit UART realization on Verilog HDL.

  Language:Verilog7517

• damdoy/ice40_ultraplus_examples

  Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation

  Language:Verilog24344

• AngeloJacobo/UberDDR3

  Opensource DDR3 Controller

  Language:Verilog18330

• sergeykhbr/riscv_vhdl

  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

  Language:Verilog620102

• XUANTIE-RV/wujian100_open

  IC design and development should be faster，simpler and more reliable

  Language:Verilog1.9k571

• pConst/basic_verilog

  Must-have verilog systemverilog modules

  Language:Verilog1.6k371

• SpinalHDL/VexRiscv

  A FPGA friendly 32 bit RISC-V CPU implementation

  Language:Assembly2.4k411