choucl

Pinned Repositories

CASend
Lightweight, Easy-to-use, Encrypted File Transfer Tool
Language:C00
DrawBot
LINE bot to draw graph
Language:Python00
FPGA-DSP
Language:C31
FPGA-SHA256
Language:Verilog20
FPGA-TrafficLight
NCKU FPGA course homework 1. Implementing traffic light simulation on PYNQ-Z2
Language:Verilog20
oboe
Oboe Bluespec Out-of-order Engine
Language:Bluespec00
TransforMAP
Modified version of the TransforMAP model from "TransforMAP: Transformer for Memory Access Prediction" (Pengmiao Zhang, et al.)
Language:Python4 2 00
solder-joint-detection
Synopsys ARC competition. Used for detecting defect solder joint. Implemented by pruned yolov3-tiny on himax WE-I plus.
Language:C++60
blokus-duo-tui
Online Blockus Duo game in terminal user interface.
Language:C2 1 00
RTOS-Project-2023-riscv-freertos-on-pynq
Porting FreeRTOS to a RISC-V based system on PYNQ-Z2
Language:C7 1 00

choucl's Repositories

choucl/TransforMAP
Modified version of the TransforMAP model from "TransforMAP: Transformer for Memory Access Prediction" (Pengmiao Zhang, et al.)
Language:Python4 2 00
choucl/FPGA-DSP
Language:C31
choucl/FPGA-SHA256
Language:Verilog20
choucl/FPGA-TrafficLight
NCKU FPGA course homework 1. Implementing traffic light simulation on PYNQ-Z2
Language:Verilog20
choucl/FPGA-Set
Language:Verilog10
choucl/FPGA-Sorting
Language:C10
choucl/riscv-arm-asm-comparator
Tool for comparing RISC-V and Arm64 assembly code difference with the same program
Language:C1
choucl/CASend
Lightweight, Easy-to-use, Encrypted File Transfer Tool
Language:C00
choucl/DrawBot
LINE bot to draw graph
Language:Python00
choucl/oboe
Oboe Bluespec Out-of-order Engine
Language:Bluespec00
choucl/AstroNvimConfig
Language:Lua
choucl/async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
choucl/BSV_Tutorial_cn
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。
Language:Bluespec
choucl/Dotfiles
Linux dot files with choucl configurations
Language:Lua
choucl/Favo-Solver
Language:Java
choucl/FPGA-BRAM
Language:C
choucl/FPGA-BreathingLight
Language:Verilog
choucl/ibex_system_on_pynq
Combine the ibex core with AXI interface of PULP platform
Language:Tcl1
choucl/JudgeServer
Language:Python
choucl/nvim
Neovim configuration of yuyu's
Language:Lua
choucl/nvim-basic-ide
This is my attempt at a basic stable starting point for a Neovim IDE.
Language:Lua
choucl/OnlineJudge
open source online judge based on Vue, Django and Docker.
Language:Python
choucl/OnlineJudgeFE
A multiple pages app built for OnlineJudge
Language:Vue