In this homework, you are asked to use Cadence Innovus to complete the P&R (Place and Route) flow for a given synthesized standard-cell design. The goal is to acquaint you with Innovus and the P&R flow. Besides, you are encouraged to try to optimize timing, total area of chip, and total wire length without violating any timing or DRC constraints.
In this homework, you are asked to implement "Fiduccia–Mattheyses Algorithm" to solve the problem of two-way min-cut partitioning.
In this homework, you are asked to adapt and implement an existing algorithm, published in the DAC-86 paper entitled "A New Algorithm for Floorplan Design" by Wong and Liu, for solving the fixed-outline slicing floorplan design problem with a set of hard blocks.
In this homework, you are asked to adapt and implement an existing algorithm, published in the ISPD-08 paper entitled “Abacus: fast legalization of standard cell circuits with minimal movement” by Spindler, Schlichtmann and Johannes, to legalize a given global placement result with minimal total displacement (measured by Euclidean distance).
In this homework, you are asked to write programs to place and route some analog circuits, and you need to output the results in the DEF (Design Exchange File) format.