vlsi-physical-design

OpenTimer/OpenTimer

A High-performance Timing Analysis Tool for VLSI Systems

AUCOHL/DFFRAM

Standard Cell Library based Memory Compiler using FF/Latch cells

cuhk-eda/dr-cu

Dr. CU, VLSI Detailed Routing Tool Developed by CUHK

OpenTimer/Parser-Verilog

A Standalone Structural Verilog Parser

luckyrantanplan/nthu-route

VLSI EDA Global Router

lip6/coriolis

Coriolis VLSI EDA Tool (LIP6)

OpenTimer/Parser-SPEF

A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

AngeloJacobo/OpenLANE-Sky130-Physical-Design-Workshop

Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130

ieee-ceda-datc/RDF-2019

DATC RDF

chengengjie/salt

Steiner Shallow-Light Tree for VLSI Routing

twweeb/VLSI-Physical-Design-Automation

Courseworks of CS6165 VLSI Physical Design Automation, NTHU.

shariethernet/Physical-Design-with-OpenLANE-using-SKY130-PDK

This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In this project, a PicoRV32a SoC is taken and then the RTL to GDSII Flow is implemented with Openlane using Skywater130nm PDK. Custom-designed standard cells with Sky130 PDK are also used in the flow. Timing Optimisations are carried out. Slack violations are removed. DRC is verified

ShonTaware/OpenSource_Physical_Design

This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK

andrsmllr/magic_vlsi_examples

Some simple examples for the Magic VLSI physical chip layout tool.

hibagus/64pointFFTProcessor

Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.

jinwookjungs/lefdef_util

A LEF/DEF Utility.

fayizferosh/yosys-tcl-ui-report

5 Day TCL begginer to advanced training workshop by VSD

jnestor/CADApps

VLSI CAD Algorithm Visualizations implemented as Java Applications

UdayaShankarS/TCL-Scripting

Examples of the TCL Scripts for different purposes and for VLSI Physical Design are provided here for your reference

aasthadave9/Advanced-Physical-Design-Using-OpenLANE-Sky130

This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an opensource RTL2GDS flow using OpenLANE and opensource PDK provided by Google/SkyWater130

curry0622/VLSI-Physical-Design-Automation

NTHU CS6135 VLSI Physical Design Automation (2022 Fall)

ganeshgore/spydrnet-physical

This is a SpyDrNet Plugin for a physical design related transformations

en9inerd/SimAn

Standard cell placement (global and detailed) tool based on modified algorithm “simulated annealing”

harshithsn/Universal-Shift-Register

This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-source EDA tool which gives RTL to GDSII flow.

meeeeet/RTL-to-GDS-Implementation-of-SerDes

lip6/alliance

Alliance VLSI CAD Tools (LIP6)

jnestor/PlacementApp

Animation of VLSI Placement/Floorplanning using Simulated Annealing or Iterative Improvement

Koyama-Tsubasa/VLSI_Physical_Design_Automation

Coursework of NTHU CS613500 VLSI Physical Design Automation

srgrr/CellRouter

A SAT-Based cell router.

trojanink/vlsi-cmos-inverter-design-magic

VLSI Design, Magic, OpenCircuitDesign,CMOS VLSI Design, CMOS Inverter Magic

virginrobotics/5-Stage-2.92-Ghz-CMOS-VCO

This is a documentation of the steps involved in designing a VCO on the SYNOPSYS Custom Compiler - 28nm PDK

enzoleo/RePlAce

A customized placer based on the RePlAce global placement tool.

ieee-ceda-datc/datc-rdf

IEEE DATC Robust Design Flow 2021.

Sooryakiran/Domain-Specific-Hardware-Accelerator-VLSI-CAD-Project

Domain Specific Hardware Accelerators - VLSI CAD Project

VardhanSuroshi/VLSI-ASIC-Design-Flow

This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out