dineshannayya/riscduino

Issues

• ctech_clk_buf in aes_top

  #32 opened 4 months ago by redpanda3
  0

• Error while running riscv_regress test

  #29 opened 10 months ago by Ajay-2204
  1

• Iverilog Version

  #31 opened 5 months ago by redpanda3
  8

• Issue with the installation of docker

  #30 opened 5 months ago by advaneharshal
  1

• Discrepencies in the readme.

  #28 opened a year ago by govardhnn
  0

• Where to buy a riscduino board?

  #27 opened a year ago by redpanda3
  2

• linting issue

  #26 opened a year ago by shanu101
  1

• issue with openlane root of riscvduino

  #25 opened a year ago by Vinayakamk
  0

• How can I program the RISCDUINO SOC?

  #21 opened a year ago by Aman-ECE
  6

• Discrepencies in the readme.

  #24 opened a year ago by iamkarthikbk
  3

• Document ADC Shortcomings

  #23 opened 2 years ago by xobs
  1

• RISCV compilation in macOS Apple Silicon

  #22 opened 2 years ago by pavand96
  0

• Problems with ‘make user_project_wrapper'

  #19 opened 2 years ago by pengpeng-lian
  1

• access latency about the sky130_sram?

  #18 opened 2 years ago by clp510
  2

• Did you download the latest version of your riscduino, which is the latest openroad tool? Also I'm having some problems with make

  #17 opened 2 years ago by pengpeng-lian
  7

• PDN probelm

  #16 opened 2 years ago by pengpeng-lian
  3

• About the change of FP_SIZING from ABSOLUTE to RELATIVE

  #15 opened 2 years ago by pengpeng-lian
  2

• question about clock skew adjust

  #14 opened 2 years ago by clp510
  3

• When I try to open the def\lef file with <openroad>, I have problems

  #13 opened 2 years ago by pengpeng-lian
  6

• It feels like there is something wrong with the code（openlane/pinmux/config.tcl.tcl）

  #12 opened 2 years ago by pengpeng-lian
  1

• openlane/Module call problem

  #11 opened 2 years ago by pengpeng-lian
  7

• Clock speed?

  #1 opened 3 years ago by elimisteve
  2

• Die status

  #2 opened 3 years ago by Sya0
  2

• PDK path error

  #3 opened 3 years ago by Sya0
  7

• Openlane implementation error

  #4 opened 3 years ago by Sya0
  13

• FPU Integration

  #5 opened 2 years ago by navan93
  2

• riscduino soc

  #6 opened 2 years ago by RanChenRivai
  2

• MPW-5 single core git version

  #7 opened 2 years ago by clp510
  5

• caravel soc & riscduino soc memory mapping

  #8 opened 2 years ago by Yuxiang-Davion
  2

• About caravel soc wishbone protocol

  #9 opened 2 years ago by Yuxiang-Davion
  2

• SystemVerilog support by yosys

  #10 opened 2 years ago by RanChenRivai
  1