This repository gathers several basic modules to handle CDC in a design.
More information about the modules can be found here:
- IO debouncer
- Simple synchronization thru 2 FFDs
- Pulse synchronizer
- Pulse synchronizer with handshake
- Data bus synchronizer with recirculation mux
All the modules are described in verilog 2001 at RTL level, compatible with SystemVerilog. They can be used either for ASIC or FPGA, being technology agnostic.
All the sources are tested with unit tests located in sim folder to illustrate their behaviors. Simulation relies on SVUT and Icarus Verilog.
An asynchronous dual-clock FIFO is added as submodule or can be found here.
Follows a list of interesting documents explaining in depth CDC topics:
- http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf
- https://zipcpu.com/blog/2017/10/20/cdc.html
- https://www.edn.com/synchronizer-techniques-for-multi-clock-domain-socs-fpgas/
- https://web.stanford.edu/class/ee183/handouts/synchronization_pres.pdf
- https://www.eetimes.com/understanding-clock-domain-crossing-issues/#