drgarbi

Digital Design Engineer @ Chipus Microelectronics

Chipus MicroelectronicsCuritiba, PR

Pinned Repositories

verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
Language:C++1.3k 49 949200
async_fifo
Asynchronous FIFO implementation in Verilog
Language:SystemVerilog00

drgarbi's Repositories

drgarbi/async_fifo
Asynchronous FIFO implementation in Verilog
Language:SystemVerilog00