emruiz

emruiz's Stars

• olofk/corescore

  CoreScore

  Language:Verilog13540

• olofk/observer

  Language:Verilog403

• openhwgroup/core-v-cores

  CORE-V Family of RISC-V Cores

  20615

• olofk/serv

  SERV - The SErial RISC-V CPU

  Language:Verilog1.4k188

• sergeykhbr/riscv_vhdl

  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

  Language:Verilog624103

• YosysHQ/picorv32

  PicoRV32 - A Size-Optimized RISC-V CPU

  Language:Verilog3.1k755

• wrongbaud/hackaday-u

  Course materials for hackaday.io Ghidra training

  Language:C37382

• Gaze-At/DS1054

  GazeAtDS1054: Viewer for Rigol DS1054Z via USB or TCP. Runs on Linux Distros using PyVisa

  943

• hdl/awesome

  A curated list of awesome resources for HDL design and verification

  Language:Shell13918

• ComplianceAsCode/content

  Security automation content in SCAP, Bash, Ansible, and other formats

  Language:Shell2.2k696

• magic-wormhole/magic-wormhole

  get things from one computer to another, safely

  Language:Python20.3k641

• joembedded/JesFs

  Jo's Embedded Serial File System (for Standard Serial NOR-Flash)

  Language:C17931

• Geontech/fins

  Firmware IP Node Specification (FINS) Code Generator

  Language:VHDL61

• chriskiehl/Gooey

  Turn (almost) any Python command line program into a full GUI application with one line

  Language:Python20.6k1k

• marysaka/ghidra_falcon

  Support of Nvidia Falcon processors for Ghidra

  Language:Java647

• xyzz/ghidra-mep

  Toshiba MeP processor module for GHIDRA

  Language:Assembly706

• James-Yu/LaTeX-Workshop

  Boost LaTeX typesetting efficiency with preview, compile, autocomplete, colorize, and more.

  Language:TypeScript10.7k533

• NationalSecurityAgency/ghidra

  Ghidra is a software reverse engineering (SRE) framework

  Language:Java51.6k5.9k

• micropython/micropython

  MicroPython - a lean and efficient Python implementation for microcontrollers and constrained systems

  Language:C19.4k7.8k

• SpinalHDL/SpinalHDL

  Scala based HDL

  Language:Scala1.7k331

• Elphel/vdt-plugin

  mirror of https://git.elphel.com/Elphel/vdt-plugin

  Language:Java151

• vmware-archive/cascade

  A Just-In-Time Compiler for Verilog from VMware Research

  Language:C++43544

• wd5gnr/tbgen

  Generate testbench for your verilog module.

  Language:Python129

• djformby/GRFICS

  Graphical Realism Framework for Industrial Control Simulations

  Language:C++21354

• bperez77/xilinx_axidma

  A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.

  Language:C469230

• KastnerRG/pp4fpgas

  Parallel Programming for FPGAs -- An open-source high-level synthesis book

  Language:TeX793148

• f4pga/prjxray

  Documenting the Xilinx 7-series bit-stream format.

  Language:Python774150

• unicorn-engine/unicorn

  Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)

  Language:C7.6k1.3k

• ossia/score

  ossia score, an interactive sequencer for the intermedia arts

  Language:C++1.5k104

• jopohl/urh

  Universal Radio Hacker: Investigate Wireless Protocols Like A Boss

  Language:Python11k872