evg-sin

evg-sin's Stars

• nothings/stb

  stb single-file public domain libraries for C/C++

  Language:C26.7k6228307.7k

• viatsko/awesome-vscode

  🎨 A curated list of delightful VS Code packages and resources.

  Language:JavaScript25k488491.2k

• videolan/vlc

  VLC media player - All pull requests are ignored, please use MRs on https://code.videolan.org/videolan/vlc

  Language:C14k58105.1k

• flipperdevices/flipperzero-firmware

  Flipper Zero firmware source code

  Language:C12.7k2861.1k2.7k

• kislyuk/argcomplete

  Python and tab completion, better together.

  Language:Python1.4k35278134

• vortexgpgpu/vortex

  Language:Verilog1.2k38114257

• MaJerle/c-code-style

  Recommended C code style and coding rules for standard C99 or later

  Language:Python1k546231

• happyfish100/libfastcommon

  c common functions library extracted from my open source project FastDFS. this library is very simple and stable. functions including: string, logger, chain, hash, socket, ini file reader, base64 encode / decode, url encode / decode, fast timer, skiplist, object pool etc. detail info please see the c header files.

  Language:C8957438531

• huawenyu/Design-Patterns-in-C

  Practical design patterns in C

  Language:C412301114

• lawrie/fpga_pio

  An attempt to recreate the RP2040 PIO in an FPGA

  Language:Verilog28919529

• mattvenn/awesome-opensource-asic-resources

  28623237

• zeroasiccorp/switchboard

  Communication framework for RTL simulation and emulation.

  Language:Python26075620

• troyguo/awesome-dv

  Awesome ASIC design verification

  24911162

• openasic-org/xk265

  xk265：HEVC/H.265 Video Encoder IP Core (RTL)

  Language:Verilog22618472

• gsmecher/minimax

  Minimax: a Compressed-First, Microcoded RISC-V CPU

  Language:Verilog20110613

• francof2a/fxpmath

  A python library for fractional fixed-point (base 2) arithmetic and binary manipulation with Numpy compatibility.

  Language:Python18177421

• WangXuan95/FPGA-FixedPoint

  A Verilog fixed-point lib: custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。

  Language:Verilog1285021

• NXP/i3c-slave-design

  MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.

  Language:Verilog106213833

• WangXuan95/FPGA-Gzip-compressor

  FPGA-based GZIP (deflate) compressor. Input raw data and output standard GZIP format (as known as .gz file format). 基于FPGA的GZIP压缩器。输入原始数据，输出标准的GZIP格式，即常见的 .gz / .tar.gz 文件的格式。

  Language:Verilog934519

• Bearzeng/h.265_encoder

  Language:Verilog7812238

• aiminickwong/H264

  H264视频解码verilog实现

  Language:Verilog766038

• zero-day-labs/riscv-iommu

  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0

  Language:SystemVerilog7352814

• manish-kj/PACoGen

  PACoGen: Posit Arithmetic Core Generator

  Language:Verilog635115

• rickyzheng/uffs

  UFFS - Ultra low cost Flash File System

  Language:C446225

• openasic-org/xkDLA

  xkDLA：XinKai Deep Learning Accelerator (RTL)

  Language:Verilog25406

• freecores/nova

  H.264/AVC Baseline Decoder

  Language:Verilog146

• catkira/complex_multiplier

  HDL code for a complex multiplier with AXI stream Interface

  Language:Python13402

• olofk/qerv

  Language:Verilog12431

• VSHEV92/Papers_STA

  Language:Tcl5100

• hellgate202/img_proc_lib

  Language:SystemVerilog11