f4pga/ideas

Issues

• RTL Schematic View

  #41 opened 5 years ago by drom
  42

• Deterministic/reproducible builds

  #67 opened 2 years ago by walling
  2

• Open FPGA for absolute beginners

  #52 opened 4 years ago by acomodi
  6

• Lowlevel LLVM-like language as HDL middle layer

  #19 opened 6 years ago by XVilka
  105

• Using Edalize to drive f4pga

  #66 opened 3 years ago by olofk
  1

• move to chipalliance org and include ASIC projects?

  #62 opened 3 years ago by proppy
  0

• Formal Verification

  #60 opened 4 years ago by andrewb1999
  2

• Create a "common configuration" git repository which is auto-merged into SymbiFlow projects

  #51 opened 5 years ago by mithro
  8

• Support for cheapest FPGAs on the market

  #39 opened 5 years ago by Harvie
  11

• Add SymbiFlow tooling to openSUSE

  #59 opened 4 years ago by mark-stopka
  2

• Community issue / bounty tracker

  #58 opened 4 years ago by bluecmd
  1

• HPC and OpenCL around SymbiFlow stack

  #57 opened 4 years ago by manili
  3

• Convert the Verilog to Routing test runner from Perl to Python

  #16 opened 6 years ago by mithro
  8

• Create a symbiflow-sphinx-docs-common repository

  #49 opened 5 years ago by mithro
  11

• Getting started with embedded RISC-V tutorial

  #33 opened 6 years ago by mgielda
  2

• SymbiFlow projects documentation audit

  #56 opened 4 years ago by kgugala
  1

• Create a series of user stories documents

  #55 opened 4 years ago by kgugala
  0

• SymbiFlow ecosystem map

  #54 opened 4 years ago by acomodi
  0

• Add Contributing Guide to SymbiFlow projects

  #53 opened 4 years ago by kgugala
  0

• Updated the repositories to comply with the current copyright best practices

  #47 opened 5 years ago by mithro
  4

• Add an .editorconfig file to all SymbiFlow repositories

  #50 opened 5 years ago by mithro
  4

• RFC: Creating a synthesis or PnR benchmark

  #48 opened 5 years ago by TheProgrammerIncarnate
  3

• Symbiflow package manager

  #15 opened 7 years ago by dvc94ch
  8

• Add common ASIC/FPGA file formats to GitHub/linguist

  #46 opened 5 years ago by mithro
  0

• improve WaveDrom

  #45 opened 5 years ago by drom
  0

• SystemVerilog parser using Tree-Sitter

  #44 opened 5 years ago by drom
  0

• Streaming VCD parser

  #43 opened 5 years ago by drom
  0

• Render LUT diagram

  #42 opened 5 years ago by drom
  1

• Support Xilinx XC9500XL CPLD series

  #38 opened 5 years ago by spth
  1

• Improve the visual representation of the placement done by VTR

  #40 opened 5 years ago by tmichalak
  0

• Participate in Google Summer of Code

  #22 opened 6 years ago by XVilka
  8

• Setup an Open Collective

  #37 opened 5 years ago by XVilka
  0

• Getting started with Debian Linux on RISC-V with SymbiFlow tutorial

  #35 opened 6 years ago by mgielda
  8

• Get LiteX/VexRiscv supported in upstream Zephyr and update RISC-V Getting Started Guide

  #28 opened 5 years ago by mgielda
  2

• Figure out automated testing of Sphinx code snippets in SymbiFlow tutorials

  #32 opened 5 years ago by mgielda
  3

• Getting started with Buildroot Linux on RISC-V with SymbiFlow tutorial

  #34 opened 6 years ago by mgielda
  1

• Improve FASM documentation to boost adoption of the standard

  #36 opened 6 years ago by mgielda
  0

• Get LiteX/minerva supported in upstream Zephyr RTOS

  #29 opened 6 years ago by mgielda
  0

• Get Murax supported in upstream Zephyr RTOS

  #30 opened 6 years ago by mgielda
  0

• Get PicoSoC supported in upstream Zephyr RTOS

  #31 opened 6 years ago by mgielda
  0

• Standardize formatting across all repos

  #27 opened 6 years ago by elms
  0

• Create a really good library for parsing / producing SDF files

  #17 opened 6 years ago by mithro
  13

• Testing on hardware

  #25 opened 6 years ago by elms
  5

• Create a Python library for generating VtR arch.xml files

  #23 opened 6 years ago by mithro
  3

• Verilog IDE based on Qt Creator integrated with SymbiFlow

  #21 opened 6 years ago by rochus-keller
  3

• Standardize or translate between different database formats

  #26 opened 6 years ago by elms
  0

• Join the forces with The OpenROAD project

  #24 opened 6 years ago by XVilka
  1

• Verilog AST format

  #20 opened 6 years ago by drom
  8

• Create Python library for parsing / producing BLIF (and eBLIF) files

  #18 opened 6 years ago by mithro
  7

• Package all of SymbiFlow dependencies into a conda repository

  #14 opened 7 years ago by mithro
  2