/0010-and-100-Sequence-Detector

Mealy Machine with VHDL

Primary LanguageVHDL

0010-and-100-Sequence-Detector

Mission

To implement sequence detector which investigates input w and will produce the output z if:

  1. w is "0010" during last 4 consecutive clock cycles, or
  2. w is "100" during last 3 consecutive clock cycles.

Sequence detector should be negative-edge triggered Mealy machine with minimum number of states.

Minimized state diagram

mealystates

Minimized state table

statetable

Using

Software: Vivado Xilinx 2020.1

Hardware: Basys 3 Artix-7 FPGA Board