ice40?
peepo opened this issue · 6 comments
David
is ice40 permanently stalled?
I do appreciate you are heavily committed on other open source initiatives!!
have potential interest and/or project, any chance of a headsup?
thanks again
CSI-2 input is working, no immediate plans for CSI-2 output. Happy to help others take this on though.
What does 'CSI-2 input is working' imply?
what is the output?
and setup?
and limitations: which ice40? I would expect any cannot fulfill 4K 30fps
Could you please add a bit more info?
I am keen to have a go, but would benefit from further detail
I have written documentation, so once I have working, can provide pull request
Do you have any stills (or video?) output
Are any especial boards required, ie ice40 to RPi V2 camera
thanks again!
I would also love to know how to get the ice40 setup working.
When using MIPI cameras with the Raspberry Pi or e.g. the Arduino Vidor, it seems that an SPI channel is used to set up the camera. From what I can see there is nothing like that here. Is it not necessary for basic functionality, or do I need some more IP blocks to take care of that?
Some instructions for a "bare minimum" ice40 setup (including some notes on hardware; i.e. the components/custom design that you have been using) would be super helfpul.
Thanks a lot!
When using MIPI cameras with the Raspberry Pi or e.g. the Arduino Vidor, it seems that an SPI channel is used to set up the camera. From what I can see there is nothing like that here. Is it not necessary for basic functionality, or do I need some more IP blocks to take care of that?
It is almost always I²C, not SPI, just with a name to get round tedious trademark issues. You don't necessarily need an IP block for this - the MARLANN ctrlsoc example bitbangs it from a picorv32 softcore, see https://github.com/SymbioticEDA/MARLANN/blob/master/demo/camera/cameraif.v#L114-L154 and the software side https://github.com/SymbioticEDA/MARLANN/blob/master/demo/camera/camera.c#L21-L162
Hi! this Verilog code package has issues with place and routing on the icebreaker board (ICE40UP5k) through iCECube2, is this because LVDS DDR inputs are hardcoded to map to Bank3 of ice40 devices, and of the icebreaker board there is only banks 0,1,and 2?
thanks, J