Issues
- 4
- 3
- 3
Is vivado indirectly required?
#82 opened by Kreijstal - 3
Error when adding PLLE2_ADV in xc7a35
#77 opened by jtplaarj - 1
Site_type Ingestion Confusion
#81 opened by fred-freeman - 8
FDRE_1 can't be written out to fasm file
#65 opened by jrsa - 3
Placer does not terminate for example design
#73 opened by hansfbaier - 2
- 0
One chipdb, multiple package
#70 opened by trabucayre - 0
Failure in generating xczu7ev.bba
#68 opened by burntfalafel - 0
router2 does not stop when it visited the source wire when routing backwards
#58 opened by hansfbaier - 2
- 3
chip-db (bba or bin) files missing
#47 opened by zipotron - 0
- 1
Cannot use OSERDESE2 in MASTER-SLAVE configuration to support 10-to-1 bit serialization
#46 opened by jhladik - 2
`bbaexport.py` fails for `xc7a35t`
#35 opened by ajelinski - 1
Constraints issue using generated chipdb file
#42 opened by Pocketkid2 - 1
bbaexport.jar compile failed!
#37 opened by the-centry - 0
- 4
Placer fails with long CARRY4 chains
#34 opened by kazkojima - 2
- 6
segmentation fault
#32 opened by KiranKanchi - 2
ERROR: Unable to place cell: no Bels remaining of type 'MMCME2_ADV_MMCME2_ADV'
#27 opened by MJoergen - 1
bbasm missing endian argument in documentation
#25 opened by LAK132 - 14
- 5
Instantiation of Xilinx PS hard IP
#24 opened by ilesser - 6
Incorrect FASM lines related to SERDES
#21 opened by acomodi - 2
Is Vivavo 2017.2 required?
#19 opened by ilesser - 3
X-Ray Database incompatible to nextpnr-xilinx FASM
#17 opened by Haini - 2
Exception when --chipdb argument is not supplied
#11 opened by Xiretza - 3
- 4
SIGBUS when running nextpnr-xilinx
#4 opened by fallen - 0
Unable to compile Artix-7 example
#6 opened by Xiretza